📄 xllp_ethernet.h
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*/
#define XLLP_LAN91C111_BAR_A_BITS (0xFFU << 8)
/*
*******************************************************************************
* Control Register - Bank 1 - Offset 12
*******************************************************************************
*/
#define XLLP_LAN91C111_CTR_STORE (0x1U << 0)
#define XLLP_LAN91C111_CTR_RELOAD (0x1U << 1)
#define XLLP_LAN91C111_CTR_EEPROM (0x1U << 2)
#define XLLP_LAN91C111_CTR_TE_ENABLE (0x1U << 5)
#define XLLP_LAN91C111_CTR_CR_ENABLE (0x1U << 6)
#define XLLP_LAN91C111_CTR_LE_ENABLE (0x1U << 7)
#define XLLP_LAN91C111_CTR_AUTO_RELEASE (0x1U << 11)
#define XLLP_LAN91C111_CTR_RCV_BAD (0x1U << 14)
/*
*******************************************************************************
* Bank 2 Register Map in I/O Space
*******************************************************************************
*/
#define XLLP_LAN91C111_MMU 0 // MMU Command Register
#define XLLP_LAN91C111_PNR 2 // Packet Number Register
#define XLLP_LAN91C111_ARR 3 // Allocation Result Register
#define XLLP_LAN91C111_FIFO 4 // FIFO Ports Register
#define XLLP_LAN91C111_POINTER 6 // Pointer Register
#define XLLP_LAN91C111_DATA_HIGH 8 // Data High Register
#define XLLP_LAN91C111_DATA_LOW 10 // Data Low Register
#define XLLP_LAN91C111_INT_STATS 12 // Interrupt Status Register - RO
#define XLLP_LAN91C111_INT_ACK 12 // Interrupt Acknowledge Register -WO
#define XLLP_LAN91C111_INT_MASK 13 // Interrupt Mask Register
/*
*******************************************************************************
* MMU Command Register - Bank 2 - Offset 0
*******************************************************************************
*/
#define XLLP_LAN91C111_MMUCR_NO_BUSY (0x1U << 0)
#define XLLP_LAN91C111_MMUCR_ALLOC_TX (0x1U << 5) // XYZ = 001
#define XLLP_LAN91C111_MMUCR_RESET_MMU (0x2U << 5) // XYZ = 010
#define XLLP_LAN91C111_MMUCR_REMOVE_RX (0x3U << 5) // XYZ = 011
#define XLLP_LAN91C111_MMUCR_REM_REL_RX (0x4U << 5) // XYZ = 100
#define XLLP_LAN91C111_MMUCR_RELEASE_RX (0x5U << 5) // XYZ = 101
#define XLLP_LAN91C111_MMUCR_RELEASE_TX (0x5U << 5) // XYZ = 101
#define XLLP_LAN91C111_MMUCR_ENQUEUE (0x6U << 5) // XYZ = 110
#define XLLP_LAN91C111_MMUCR_RESET_TX (0x7U << 5) // XYZ = 111
/*
*******************************************************************************
* Packet Number Register - Bank 2 - Offset 2
*******************************************************************************
*/
#define XLLP_LAN91C111_PNR_TX (0x3FU << 0)
/*
*******************************************************************************
* Allocation Result Register - Bank 2 - Offset 3
*******************************************************************************
*/
#define XLLP_LAN91C111_ARR_ALLOC_PN (0x3FU << 0)
#define XLLP_LAN91C111_ARR_FAILED (0x1U << 7)
/*
*******************************************************************************
* FIFO Ports Register - Bank 2 - Offset 4
*******************************************************************************
*/
#define XLLP_LAN91C111_FIFO_TX_DONE_PN (0x3FU << 0)
#define XLLP_LAN91C111_FIFO_TEMPTY (0x1U << 7)
#define XLLP_LAN91C111_FIFO_RX_DONE_PN (0x3FU << 8)
#define XLLP_LAN91C111_FIFO_RXEMPTY (0x1U << 15)
/*
*******************************************************************************
* Pointer Register - Bank 2 - Offset 6
*******************************************************************************
*/
#define XLLP_LAN91C111_PTR_LOW (0xFFU << 0)
#define XLLP_LAN91C111_PTR_HIGH (0x7U << 8)
#define XLLP_LAN91C111_PTR_NOT_EMPTY (0x1U << 11)
#define XLLP_LAN91C111_PTR_ETEN (0x1U << 12)
#define XLLP_LAN91C111_PTR_READ (0x1U << 13)
#define XLLP_LAN91C111_PTR_AUTO_INCR (0x1U << 14)
#define XLLP_LAN91C111_PTR_RCV (0x1U << 15)
#define XLLP_LAN91C111_PTR_RX_FRAME (XLLP_LAN91C111_PTR_RCV | \
XLLP_LAN91C111_PTR_AUTO_INCR | \
XLLP_LAN91C111_PTR_READ)
#define XLLP_LAN91C111_PTR_RX_FRAME_NO_AUTO_INC (XLLP_LAN91C111_PTR_RCV | XLLP_LAN91C111_PTR_READ)
/*
*******************************************************************************
* Data Register - Bank 2 - Offset 8
*******************************************************************************
*/
#define XLLP_LAN91C111_CONTROL_CRC (0x1U << 4) // CRC bit
#define XLLP_LAN91C111_CONTROL_ODD (0x1U << 5) // ODD bit
/*
*******************************************************************************
* Interrupt Status Register - Bank 2 - Offset 12
*******************************************************************************
*/
#define XLLP_LAN91C111_IST_RCV_INT (0x1U << 0)
#define XLLP_LAN91C111_IST_TX_INT (0x1U << 1)
#define XLLP_LAN91C111_IST_TX_EMPTY_INT (0x1U << 2)
#define XLLP_LAN91C111_IST_ALLOC_INT (0x1U << 3)
#define XLLP_LAN91C111_IST_RX_OVRN_INT (0x1U << 4)
#define XLLP_LAN91C111_IST_EPH_INT (0x1U << 5)
#define XLLP_LAN91C111_IST_ERCV_INT (0x1U << 6)
#define XLLP_LAN91C111_IST_MD_INT (0x1U << 7)
/*
*******************************************************************************
* Interrupt Acknowledge Register - Bank 2 - Offset 12
*******************************************************************************
*/
#define XLLP_LAN91C111_ACK_TX_INT (0x1U << 1)
#define XLLP_LAN91C111_ACK_TX_EMPTY_INT (0x1U << 2)
#define XLLP_LAN91C111_ACK_RX_OVRN_INT (0x1U << 4)
#define XLLP_LAN91C111_ACK_ERCV_INT (0x1U << 6)
#define XLLP_LAN91C111_ACK_MD_INT (0x1U << 7)
/*
*******************************************************************************
* Interrupt Mask Register - Bank 2 - Offset 12
*******************************************************************************
*/
#define XLLP_LAN91C111_MSK_RCV_INT (0x1U << 0)
#define XLLP_LAN91C111_MSK_TX_INT (0x1U << 1)
#define XLLP_LAN91C111_MSK_TX_EMPTY_INT (0x1U << 2)
#define XLLP_LAN91C111_MSK_ALLOC_INT (0x1U << 3)
#define XLLP_LAN91C111_MSK_RX_OVRN_INT (0x1U << 4)
#define XLLP_LAN91C111_MSK_EPH_INT (0x1U << 5)
#define XLLP_LAN91C111_MSK_ERCV_INT (0x1U << 6)
#define XLLP_LAN91C111_MSK_MD_INT (0x1U << 7)
/*
*******************************************************************************
* Bank 3 Register Map in I/O Space
*******************************************************************************
*/
#define XLLP_LAN91C111_MULTICAST0 0 // Multicast Table 0
#define XLLP_LAN91C111_MULTICAST1 1 // Multicast Table 1
#define XLLP_LAN91C111_MULTICAST2 2 // Multicast Table 2
#define XLLP_LAN91C111_MULTICAST3 3 // Multicast Table 3
#define XLLP_LAN91C111_MULTICAST4 4 // Multicast Table 4
#define XLLP_LAN91C111_MULTICAST5 5 // Multicast Table 5
#define XLLP_LAN91C111_MULTICAST6 6 // Multicast Table 6
#define XLLP_LAN91C111_MULTICAST7 7 // Multicast Table 7
#define XLLP_LAN91C111_MGMT 8 // Management Interface
#define XLLP_LAN91C111_REVISION 10 // Revision Register
#define XLLP_LAN91C111_ERCV 12 // Early Rcv Register
/*
*******************************************************************************
* Management Interface - Bank 3 -Offset 8
*******************************************************************************
*/
#define XLLP_LAN91C111_MGMT_MDO (0x1U << 0)
#define XLLP_LAN91C111_MGMT_MDI (0x1U << 1)
#define XLLP_LAN91C111_MGMT_MCLK (0x1U << 2)
#define XLLP_LAN91C111_MGMT_MDOE (0x1U << 3)
#define XLLP_LAN91C111_MGMT_MSK_CRS100 (0x3U << 14)
/*
*******************************************************************************
* Revision Register - Bank 3 - Offset 10
*******************************************************************************
*/
#define XLLP_LAN91C111_REV_REVID (0xFU << 0)
#define XLLP_LAN91C111_REV_CHIPID (0xFU << 4)
/*
*******************************************************************************
* Early RCV Register - Bank 3 - Offset 12
*******************************************************************************
*/
#define XLLP_LAN91C111_ERCV_THRESHOLD (0x1FU << 0)
#define XLLP_LAN91C111_ERCV_RCV_DISCRD (0x1U << 7)
/*
*******************************************************************************
* PHY Registers
*******************************************************************************
*/
#define XLLP_LAN91C111_CONTROL_MII_DIS 0x3000
#define XLLP_LAN91C111_CONTROL_LPBK 0x7000
/*
*******************************************************************************
* Receive Frame Status Word
*******************************************************************************
*/
#define XLLP_LAN91C111_TOO_SHORT (0x1U << 10)
#define XLLP_LAN91C111_TOO_LONG (0x1U << 11)
#define XLLP_LAN91C111_ODD_FRM (0x1U << 12)
#define XLLP_LAN91C111_BAD_CRC (0x1U << 13)
#define XLLP_LAN91C111_BROD_CAST (0x1U << 14)
#define XLLP_LAN91C111_ALGN_ERR (0x1U << 15)
#ifdef NO_BROADCAST
#define XLLP_LAN91C111_FRAME_FILTER (XLLP_LAN91C111_TOO_SHORT | \
XLLP_LAN91C111_TOO_LONG | \
XLLP_LAN91C111_BAD_CRC | \
XLLP_LAN91C111_BROD_CAST | \
XLLP_LAN91C111_ALGN_ERR)
#else
#define XLLP_LAN91C111_FRAME_FILTER (XLLP_LAN91C111_TOO_SHORT | \
XLLP_LAN91C111_TOO_LONG | \
XLLP_LAN91C111_BAD_CRC | \
XLLP_LAN91C111_ALGN_ERR)
#endif // NO_BROADCAST
/*
*******************************************************************************
* Default I/O Signature - 0x33
*******************************************************************************
*/
#define XLLP_LAN91C111_LOW_SIGNATURE (0x33U << 0)
#define XLLP_LAN91C111_HIGH_SIGNATURE (0x33U << 8)
#define XLLP_LAN91C111_SIGNATURE (XLLP_LAN91C111_HIGH_SIGNATURE | XLLP_LAN91C111_LOW_SIGNATURE)
/*
*******************************************************************************
* LAN91C111 Address Space
*******************************************************************************
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