xllp_ethernet.h

Windows CE 6.0 BSP for VOIP sample phone. Intel PXA270 platform.

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// Copyright (c) Microsoft Corporation.  All rights reserved.
//
//
// Use of this sample source code is subject to the terms of the Microsoft
// license agreement under which you licensed this sample source code. If
// you did not accept the terms of the license agreement, you are not
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// please see the license agreement between you and Microsoft or, if applicable,
// see the LICENSE.RTF on your install media or the root of your tools installation.
// THE SAMPLE SOURCE CODE IS PROVIDED "AS IS", WITH NO WARRANTIES.
//
/******************************************************************************
**
**  COPYRIGHT (C) 2000, 2001 Intel Corporation.
**
**  This software as well as the software described in it is furnished under 
**  license and may only be used or copied in accordance with the terms of the 
**  license. The information in this file is furnished for informational use 
**  only, is subject to change without notice, and should not be construed as 
**  a commitment by Intel Corporation. Intel Corporation assumes no 
**  responsibility or liability for any errors or inaccuracies that may appear 
**  in this document or any software that may be provided in association with 
**  this document. 
**  Except as permitted by such license, no part of this document may be 
**  reproduced, stored in a retrieval system, or transmitted in any form or by 
**  any means without the express written consent of Intel Corporation. 
**
**  FILENAME:       xllp_ethernet.h
**
**  PURPOSE:        This is the main header file for the LAN91C111 Ethernet
**                  Controller.
**
**
******************************************************************************/

#ifndef _xllp_ethernet_h
#define _xllp_ethernet_h

/*
*******************************************************************************
*   HEADER FILES
*******************************************************************************
*/
#include "xllp_defs.h"
#include "xllp_reg_base_os_depend.h"

#if defined(POST_BUILD)
#include <stdio.h>
#include <string.h>
#elif defined(WinCE_BUILD)
#include <windows.h>
#include <halether.h>
#endif

/*
*******************************************************************************
*    Bank Select Field
*******************************************************************************
*/
#define XLLP_LAN91C111_BANK_SELECT	    14    // Byte Offset to Bank Select Register
#define XLLP_LAN91C111_BANK_SELECT_16	7     // Word Offset to Bank Select Register
#define XLLP_LAN91C111_BANK_SELECT_32   3     // Dword Offset to Bank Select Register
#define XLLP_LAN91C111_BANKSEL_MASK     (0x7U << 0)
#define XLLP_LAN91C111_BANKSEL_SHIFT    16
#define BANK0               0x00
#define BANK1               0x01
#define BANK2               0x02
#define BANK3               0x03
#define BANK7               0x07

/*
*******************************************************************************
*    EEPROM Addresses.
*******************************************************************************
*/
#define EEPROM_MAC_OFFSET_1    0x6020   // This value is used to read IA0-1 from EEPROM
#define EEPROM_MAC_OFFSET_2    0x6021   // This value is used to read IA2-3 from EEPROM
#define EEPROM_MAC_OFFSET_3    0x6022   // This value is used to read IA4-5 from EEPROM

#define EEPROM_MAC_OFFSET_1_W  0x4020   // This value is used to write IA0-1 to EEPROM
#define EEPROM_MAC_OFFSET_2_W  0x4021   // This value is used to write IA2-3 to EEPROM
#define EEPROM_MAC_OFFSET_3_W  0x4022   // This value is used to write IA4-5 to EEPROM

/*
*******************************************************************************
*    Bank 0 Register Map in I/O Space
*******************************************************************************
*/
#define XLLP_LAN91C111_TCR          0        // Transmit Control Register
#define XLLP_LAN91C111_EPH_STATUS   2        // EPH Status Register
#define XLLP_LAN91C111_RCR          4        // Receive Control Register
#define XLLP_LAN91C111_COUNTER      6        // Counter Register
#define XLLP_LAN91C111_MIR          8        // Memory Information Register
#define XLLP_LAN91C111_RPCR         10       // Receive/PHY Control Register

/*
*******************************************************************************
*    Transmit Control Register - Bank 0 - Offset 0
*******************************************************************************
*/
#define XLLP_LAN91C111_TCR_TXENA        (0x1U << 0)
#define XLLP_LAN91C111_TCR_LOOP         (0x1U << 1)
#define XLLP_LAN91C111_TCR_FORCOL       (0x1U << 2)
#define XLLP_LAN91C111_TCR_TXP_EN       (0x1U << 3)
#define XLLP_LAN91C111_TCR_PAD_EN       (0x1U << 7)
#define XLLP_LAN91C111_TCR_NOCRC        (0x1U << 8)
#define XLLP_LAN91C111_TCR_MON_CSN      (0x1U << 10)
#define XLLP_LAN91C111_TCR_FDUPLX       (0x1U << 11)
#define XLLP_LAN91C111_TCR_STP_SQET     (0x1U << 12)
#define XLLP_LAN91C111_TCR_EPH_LOOP     (0x1U << 13)
#define XLLP_LAN91C111_TCR_SWFDUP       (0x1U << 15)

/*
*******************************************************************************
*    EPH Status Register - Bank 0 - Offset 2
*******************************************************************************
*/
#define XLLP_LAN91C111_EPHSR_TX_SUC     (0x1U << 0)
#define XLLP_LAN91C111_EPHSR_SNGL_COL   (0x1U << 1)
#define XLLP_LAN91C111_EPHSR_MUL_COL    (0x1U << 2)
#define XLLP_LAN91C111_EPHSR_LTX_MULT   (0x1U << 3)
#define XLLP_LAN91C111_EPHSR_16COL      (0x1U << 4)
#define XLLP_LAN91C111_EPHSR_SQET       (0x1U << 5)
#define XLLP_LAN91C111_EPHSR_LTX_BRD    (0x1U << 6)
#define XLLP_LAN91C111_EPHSR_TX_DEFR    (0x1U << 7)
#define XLLP_LAN91C111_EPHSR_LATCOL     (0x1U << 9)
#define XLLP_LAN91C111_EPHSR_LOST_CARR  (0x1U << 10)
#define XLLP_LAN91C111_EPHSR_EXC_DEF    (0x1U << 11)
#define XLLP_LAN91C111_EPHSR_CTR_ROL    (0x1U << 12)
#define XLLP_LAN91C111_EPHSR_LINK_OK    (0x1U << 14)
#define XLLP_LAN91C111_EPHSR_TX_UNRN    (0x1U << 15)

#define XLLP_LAN91C111_EPHSR_ERRORS     (XLLP_LAN91C111_EPHSR_SNGL_COL |    \
                                   XLLP_LAN91C111_EPHSR_MUL_COL   |    \
                                   XLLP_LAN91C111_EPHSR_16COL     |    \
                                   XLLP_LAN91C111_EPHSR_SQET      |    \
                                   XLLP_LAN91C111_EPHSR_TX_DEFR   |    \
                                   XLLP_LAN91C111_EPHSR_LATCOL    |    \
                                   XLLP_LAN91C111_EPHSR_LOST_CARR |    \
                                   XLLP_LAN91C111_EPHSR_EXC_DEF   |    \
                                   XLLP_LAN91C111_EPHSR_LINK_OK   |    \
                                   XLLP_LAN91C111_EPHSR_TX_UNRN)

/*
*******************************************************************************
*    Receive Control Register - Bank 0 - Offset 4
*******************************************************************************
*/
#define XLLP_LAN91C111_RCR_RX_ABORT     (0x1U << 0)
#define XLLP_LAN91C111_RCR_PRMS         (0x1U << 1)
#define XLLP_LAN91C111_RCR_ALMUL        (0x1U << 2)
#define XLLP_LAN91C111_RCR_RXEN         (0x1U << 8)
#define XLLP_LAN91C111_RCR_STRIP_CRC    (0x1U << 9)
#define XLLP_LAN91C111_RCR_ABORT_ENB    (0x1U << 13)
#define XLLP_LAN91C111_RCR_FILT_CAR     (0x1U << 14)
#define XLLP_LAN91C111_RCR_SOFT_RST     (0x1U << 15)

/*
*******************************************************************************
*    Counter Register - Bank 0 - Offset 6
*******************************************************************************
*/
#define XLLP_LAN91C111_ECR_SNGL_COL     (0xFU << 0)
#define XLLP_LAN91C111_ECR_MULT_COL     (0xFU << 5)
#define XLLP_LAN91C111_ECR_DEF_TX       (0xFU << 8)
#define XLLP_LAN91C111_ECR_EXC_DEF_TX   (0xFU << 12)

/*
*******************************************************************************
*    Memory Information Register - Bank 0 - OFfset 8
*******************************************************************************
*/
#define XLLP_LAN91C111_MIR_SIZE        (0x1 << 2)    // 8K bytes

/*
*******************************************************************************
*    Receive/PHY Control Register - Bank 0 - Offset 10
*******************************************************************************
*/
#define XLLP_LAN91C111_RPCR_ANEG       (0x1U << 11)
#define XLLP_LAN91C111_RPCR_DPLX       (0x1U << 12)
#define XLLP_LAN91C111_RPCR_SPEED      (0x1U << 13)

#define XLLP_LAN91C111_RPCR_LSX0A      (0x0U << 5)   // Link detected (default)
#define XLLP_LAN91C111_RPCR_LSX2A      (0x2U << 5)   // 10Mbps Link detected
#define XLLP_LAN91C111_RPCR_LSX3A      (0x3U << 5)   // Full Duplex Mode Enabled
#define XLLP_LAN91C111_RPCR_LSX4A      (0x4U << 5)   // Transmit or Receive packet occured
#define XLLP_LAN91C111_RPCR_LSX5A      (0x5U << 5)   // 100Mbps Link detected
#define XLLP_LAN91C111_RPCR_LSX6A      (0x6U << 5)   // Receive packet occured
#define XLLP_LAN91C111_RPCR_LSX7A      (0x7U << 5)   // Transmit packet occured
#define XLLP_LAN91C111_RPCR_LSX0B      (0x0U << 2)   // Link detected (default)
#define XLLP_LAN91C111_RPCR_LSX2B      (0x2U << 2)   // 10Mbps Link detected
#define XLLP_LAN91C111_RPCR_LSX3B      (0x3U << 2)   // Full Duplex Mode Enabled
#define XLLP_LAN91C111_RPCR_LSX4B      (0x4U << 2)   // Transmit or Receive packet occured
#define XLLP_LAN91C111_RPCR_LSX5B      (0x5U << 2)   // 100Mbps Link detected
#define XLLP_LAN91C111_RPCR_LSX6B      (0x6U << 2)   // Receive packet occured
#define XLLP_LAN91C111_RPCR_LSX7B      (0x7U << 2)   // Transmit packet occured

/*
*******************************************************************************
*    Bank 1 Register Map in I/O Space
*******************************************************************************
*/
#define XLLP_LAN91C111_CONFIG       0        // Configuration Register
#define XLLP_LAN91C111_BASE         2        // Base Address Register
#define XLLP_LAN91C111_IA0          4        // Individual Address Register - 0
#define XLLP_LAN91C111_IA1          5        // Individual Address Register - 1
#define XLLP_LAN91C111_IA2          6        // Individual Address Register - 2
#define XLLP_LAN91C111_IA3          7        // Individual Address Register - 3
#define XLLP_LAN91C111_IA4          8        // Individual Address Register - 4
#define XLLP_LAN91C111_IA5          9        // Individual Address Register - 5
#define XLLP_LAN91C111_GEN_PURPOSE  10       // General Address Registers
#define XLLP_LAN91C111_CONTROL      12       // Control Register

/*
*******************************************************************************
*    Configuration Register - Bank 1 - Offset 0
********************************************************************************
*/
#define XLLP_LAN91C111_CR_EXT_PHY       (0x1U << 9)
#define XLLP_LAN91C111_CR_GPCNTRL       (0x1U << 10)
#define XLLP_LAN91C111_CR_NO_WAIT       (0x1U << 12)
#define XLLP_LAN91C111_CR_EPH_POWER_EN  (0x1U << 15)

/*
*******************************************************************************
*    Base Address Register - Bank 1 - Offset 2
*******************************************************************************