📄 xlli_lowlev_init.s
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;
;
; Use of this sample source code is subject to the terms of the Microsoft
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; THE SAMPLE SOURCE CODE IS PROVIDED "AS IS", WITH NO WARRANTIES.
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;
; Copyright 2002-2003 Intel Corporation All Rights Reserved.
;**
;** Portions of the source code contained or described herein and all documents
;** related to such source code (Material) are owned by Intel Corporation
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;** Some portion of the Materials may be copyrighted by Microsoft Corporation.
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;
;*********************************************************************************
;
; FILENAME: xlli_LowLev_Init.s
;
; PURPOSE: Provides low Level init procedures written specifically for
; the Bulverde/Mainstone platform.
;
;
; LAST MODIFIED: 25-Feb-2005
;******************************************************************************
;
; The functions in this source code are called via a branch with link instruction.
; Unless otherwise specified, no system stack is assumed and no registers are preserved.
;
; NOTES:
;
; The use of these subroutines and/or the order in which they are called is, for the most part,
; arbitrary and is left up to the user. Only a few subroutines must be called in a specific order.
; For example, it makes no sense to go to virtual mode before the MMU is initialized and
; the page table is set up.... and, in order to set up the page table, memory needs to be initialized
; first.
;
INCLUDE xlli_Bulverde_defs.inc ; Bulverde specific include file
INCLUDE xlli_Mainstone_defs.inc ; Mainstone specific include file
;
AREA |text|, CODE, READONLY, ALIGN=5 ; Align =5 required for "ALIGN 32" feature to work.
;
; List of Low Level Init functions in this source code include:
;
EXPORT xlli_read_SCR ; Reads the SCR and LCDR virtural registers and places in SRAM
EXPORT xlli_GPIO_init ; Get SCR and LCDCR data and Initialize the GPIO ports
EXPORT xlli_mem_init ; Memory controller initialization
EXPORT xlli_mem_restart ; Restart memory controller
EXPORT xlli_mem_Tmax ; Sets maximum memory configuration values
EXPORT xlli_mem_Topt ; Sets optimal memory configuration values based on MemClk frequency
EXPORT xlli_intr_init ; Interrupt initialization (masks all interrupts)
EXPORT xlli_freq_change ; Frequency change sequence
EXPORT xlli_clks_init ; Initialize system clocks
EXPORT xlli_clks_init_sleepReset ; Initialize system clock after a sleep reset
EXPORT xlli_ost_init ; Initalize Operating System Timers
EXPORT xlli_icache_enable ; Enable I-Cache, D-Cache, and Branch Target Buffer
EXPORT xlli_pwrmgr_init ; Initialize the Power Manager
EXPORT xlli_setPTB ; Set the Page Tabe Base address (used for sleep resets)
EXPORT xlli_initPageTable ; Initialize Page Table for MMU unit
EXPORT xlli_MMU_init ; Initialize the Memory Management Unit
EXPORT xlli_goVirtual ; Make the transition from physical address to virtual address
EXPORT xlli_IMpwr_init ; Initialize Internal Memory for use
EXPORT GetSCR ; Returns System Configuration Register data to 'C' program caller
EXPORT xlli_setClocks ; Reads platform switchs and sets Bulverde frequencies
EXPORT xlli_getFreq ; Returns current system clock settings to 'C' program caller
EXPORT xlli_setBufImpedance ; Sets SCRAM buffer impedance (C callable)
EXPORT xlli_setBufImp ; Sets SCRAM buffer impedance (ROM callable)
;******************************************************************************
;
;
; *****************
; * *
; * xlli_read_SCR *
; * *
; *****************
;
; This subroutine will reconfigure the GPIO pins in order to read the SCR (system
; Configuration Register) and the LCDCR (LCD Configuration Register) and place this
; information into SRAM for use by other programs.
;
; Once these virtural register have been read, the GPIOs are reconfigured to their
; previous state.
;
; NOTES: Written for the Bulverde Processor on the Mainstone Development Platform.
;
; This subroutine uses and DOES NOT PRESERVE registers r1, r2, r3, r4, r5, r6, r7, r8 and r9
;
xlli_read_SCR FUNCTION
;
; Insure the RDH and PH bits on Bulverde must be clear to enable GPIO pins.
; They are sticky bits so they must be set to clear them.
;
ldr r4, =xlli_PMRCREGS_PHYSICAL_BASE
mov r2, #(xlli_PSSR_PH | xlli_PSSR_RDH) ; Set the PH and RDH bits to enable all GPIOs
str r2, [r4, #xlli_PSSR_offset] ; Enable all GPIO lines
;
; Get, and save the present GPIO settings for direction registers 0, 1 and 2
;
ldr r4, =xlli_GPIOREGS_PHYSICAL_BASE ; Get the GPIO registers base address
ldr r5, [r4, #xlli_GPDR1_offset] ; Save direction values for GPIOs [63:32]
ldr r6, [r4, #xlli_GPDR2_offset] ; Save direction values for GPIOs [95:64]
ldr r7, [r4, #xlli_GAFR1_U_offset] ; Save alt function values for GPIOs [63:48]
ldr r8, [r4, #xlli_GAFR2_L_offset] ; Save alt function values for GPIOs [79:64]
ldr r9, [r4, #xlli_GAFR2_U_offset] ; Save alt function values for GPIOs [95:80]
;
; Clear the bits of those GPIOs we need to read as inputs and write back to the GPIO
; direction registers. The alternate function bits also need to be cleared. For this
; particular code sequence "Magic Numbers" are used for the bit clear masks.
;
; To cut down on the number of registers used we'll do GPDR1 and GPDR2 now and take care of
; GPDR0 (and it's alternate function bits) later. Because this code is usually run very early
; in the boot sequence (before SDRAM is brought up) the code assumes there is no stack to
; preserve the contents of the registers used.
;
ldr r2, =0xFC000000 ; Register clear mask for GPDR1
bic r1, r5, r2 ; Clear the bits we need to read in GPDR1
str r1, [r4, #xlli_GPDR1_offset] ; Write direction values for GPIOs [63:32]
ldr r2, =0x00C02FFF ; Register clear mask for GPDR2
bic r1, r6, r2 ; Clear the bits we need to read in GPDR2
str r1, [r4, #xlli_GPDR2_offset] ; Write direction values for GPIOs [95:64]
;
; Clear the alternate function bits for the direction bits we need to look at.
;
ldr r2, =0xFFF00000 ; Register clear mask for GAFR1_U
bic r1, r7, r2 ; Clear the alt func for bits we need to read in GAFR1_U
str r1, [r4, #xlli_GAFR1_U_offset] ; Write alt function values for GPIOs [63:48]
ldr r2, =0x0CFFFFFF ; Register clear mask for GAFR2_L
bic r1, r8, r2 ; Clear the alt func for bits we need to read in GAFR2_L
str r1, [r4, #xlli_GAFR2_L_offset] ; Write alt function values for GPIOs [79:64]
ldr r2, =0x0000F000 ; Register clear mask for GAFR2_U
bic r1, r9, r2 ; Clear the alt func for bits we need to read in GAFR2_U
str r1, [r4, #xlli_GAFR2_U_offset] ; Write alt function values for GPIOs [95:80]
mov r1, #0x200
xlli_1 subs r1, r1, #1 ; Short delay required to allow the new GPIO...
bne xlli_1 ; ...settings to take effect
;
; With the GPIO direction registers set, the Platform System Configuration Register is read
; from GPIO bits 73:58 and are stored in SRAM.
; This data is placed in the UPPER 16 BITS (31:16) of this register.
;
ldr r1, [r4, #xlli_GPLR1_offset] ; Get levels for GPIOs [63:32]
mov r1, r1, LSR #10 ; Move the data 10 bits to the right
ldr r2, [r4, #xlli_GPLR2_offset] ; Get levels for GPIOs [95:64]
mov r3, r2 ; Save a copy for future reference
mov r2, r2, LSL #22 ; Move the data 22 bits to the left
orr r1, r1, r2 ; This places GPIO data bits [73:58] into bits [31:16]
ldr r2, =0xFFFF0000 ; Mask word
and r1, r1, r2 ; Make sure the bottom 16 bits are clear
;
; Restore GPDR1, GPDR2, GAFR1_U, GAFR2_L and GAFR2_U to their original values
;
str r5, [r4, #xlli_GPDR1_offset] ; Restore direction values for GPIOs [63:32]
str r6, [r4, #xlli_GPDR2_offset] ; Restore direction values for GPIOs [95:64]
str r7, [r4, #xlli_GAFR1_U_offset] ; Restore alt function values for GPIOs [63:48]
str r8, [r4, #xlli_GAFR2_L_offset] ; Restore alt function values for GPIOs [79:64]
str r9, [r4, #xlli_GAFR2_U_offset] ; Restore alt function values for GPIOs [95:80]
;
; Configure GPDR0, GAFR0_L and GAFR0_U to pick up four status bits we need from this word
; NOTE: The values in r1 and r4 must be preserved through this section of code.
;
ldr r5, [r4, #xlli_GPDR0_offset] ; Save direction values for GPIOs [31:0]
ldr r6, [r4, #xlli_GAFR0_L_offset] ; Save alt function values for GPIOs [15:0]
ldr r7, [r4, #xlli_GAFR0_U_offset] ; Save alt function values for GPIOs [31:16]
ldr r2, =0xC0084000 ; Register clear mask for GPDR0
bic r8, r5, r2 ; Clear the bits we need to read in GPDR0
str r8, [r4, #xlli_GPDR0_offset] ; Write direction values for GPIOs [31:0]
;
; Clear the alternate function bits for the direction bits we need to look at.
;
ldr r2, =0x30000000 ; Register clear mask for GAFR0_L
bic r8, r6, r2 ; Clear the alt func for bits we need to read in GAFR0_L
str r8, [r4, #xlli_GAFR0_L_offset] ; Write alt function values for GPIOs [15:0]
ldr r2, =0xF00000C0 ; Register clear mask for GAFR0_U
bic r8, r7, r2 ; Clear the alt func for bits we need to read in GAFR0_U
str r8, [r4, #xlli_GAFR0_U_offset] ; Write alt function values for GPIOs [31:16]
mov r2, #0x200
xlli_2 subs r2, r2, #1 ; Short delay required to allow the new GPIO...
bne xlli_2 ; ...settings to take effect
;
; The data that makes up the LCDCR registar (GPIO bits 87, 86, 77, 75, 74, 19, and 14) are
; stored in bits 6:0 of the PSPR. The xlli code does not use this data - it is only placed
; into the PSPR to make the data accessable to other users who can then take the data and
; store it elsewhere or simply ignore it and write over it.
;
; The SCR data is in the upper 16 bits of r1. Now the data for the LCDCR register needs
; to be assembled from data saved in r3 in addition to two bits to be read from GPIOs 31:0
; and this data needs to be ORed into r1 as well.
;
and r2, r3, #0x2000 ; isolate bit 77
mov r2, r2, LSR #9 ; Move to bit position #4
and r8, r3, #0xC00 ; Extract bits 75:74
mov r8, r8, LSR #8 ; Move GPIO bits 75:74 to bit position 3:2
orr r2, r2, r8 ; Save these two bits into r2
and r8, r3, #0xC00000 ; Extract bits 87:86
mov r8, r8, LSR #17 ; Move GPIO bits 87:86 to bit position 6:5
orr r2, r2, r8 ; Save these two bits into r2
ldr r3, [r4, #xlli_GPLR0_offset] ; Get levels for GPIOs [31:0]
mov r3, r3, LSR #14 ; Allign GPIO bit 14 with bit position 0
and r8, r3, #0x1 ; Extract this bit
orr r2, r2, r8 ; OR this bit into r2
mov r3, r3, LSR #4 ; move GPIO bit 19 into bit location 1
and r8, r3, #0x2 ; extract this bit
orr r2, r2, r8 ; OR this bit value into r2
mov r3, r3, LSR #5 ; move GPIO bits 31:30 into bit locations 8:7
and r3, r3, #0x180 ; isolate these bits
orr r2, r2, r3 ; OR this bit value into r2
;
; Restore GPDR0, GAFR0_L and GAFR0_U to their original values
;
str r5, [r4, #xlli_GPDR0_offset] ; Restore direction values for GPIOs [31:0]
str r6, [r4, #xlli_GAFR0_L_offset] ; Restore alt function values for GPIOs [15:0]
str r7, [r4, #xlli_GAFR0_U_offset] ; Restore alt function values for GPIOs [31:16]
;
; Now we need to read status from GPIOs 103, 104 and 113
;
; Configure GPDR3, GAFR3_L and GAFR3_U to pick up three status bits we need from this word
; NOTE: The values in r1 and r4 must be preserved through this section of code.
;
ldr r5, [r4, #xlli_GPDR3_offset] ; Save direction values for GPIOs [127:96]
ldr r6, [r4, #xlli_GAFR3_L_offset] ; Save alt function values for GPIOs [111:96]
ldr r7, [r4, #xlli_GAFR3_U_offset] ; Save alt function values for GPIOs [127:112]
ldr r9, =0x00020180 ; Register clear mask for GPDR3
bic r8, r5, r9 ; Clear the bits we need to read in GPDR3
str r8, [r4, #xlli_GPDR3_offset] ; Write direction values for GPIOs [127:96]
;
; Clear the alternate function bits for the direction bits we need to look at.
;
ldr r9, =0x0003C000 ; Register clear mask for GAFR3_L
bic r8, r6, r9 ; Clear the alt func for bits we need to read in GAFR3_L
str r8, [r4, #xlli_GAFR3_L_offset] ; Write alt function values for GPIOs [111:96]
ldr r9, =0x0000000C ; Register clear mask for GAFR3_U
bic r8, r7, r9 ; Clear the alt func for bits we need to read in GAFR3_U
str r8, [r4, #xlli_GAFR3_U_offset] ; Write alt function values for GPIOs [127:112]
mov r9, #0x200
xlli_15 subs r9, r9, #1 ; Short delay required to allow the new GPIO...
bne xlli_15 ; ...settings to take effect
ldr r3, [r4, #xlli_GPLR3_offset] ; Get levels for GPIOs [127:96]
;
; Restore GPDR3, GAFR3_L and GAFR3_U to their original values
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