📄 dump_eth.c
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//
// Copyright (c) Microsoft Corporation. All rights reserved.
//
//
// Use of this source code is subject to the terms of the Microsoft end-user
// license agreement (EULA) under which you licensed this SOFTWARE PRODUCT.
// If you did not accept the terms of the EULA, you are not authorized to use
// this source code. For a copy of the EULA, please see the LICENSE.RTF on your
// install media.
//
//------------------------------------------------------------------------------
//
// File: dump_eth.c
//
#include <windows.h>
#include <ceddk.h>
#include <oal.h>
#include <bcm11.h>
//------------------------------------------------------------------------------
// Local functions
static UINT8 RevertByte(UINT8 b);
//------------------------------------------------------------------------------
//
// Function: BCM11DumpETH
//
// Dump ETH registers to debug output.
//
VOID BCM11DumpETH()
{
BCM11_ETH_REGS *pETH = OALPAtoUA(BCM11_ETH_REGS_PA);
OALLog(L"\r\n");
OALLog(L"====== BCM11xx ETH Registers ======\r\n");
OALLog(L" CTRL_PORT0 = 0x%02x\r\n", (UINT8)INREG32(&pETH->CTRL_PORT0));
OALLog(L" CTRL_PORT1 = 0x%02x\r\n", (UINT8)INREG32(&pETH->CTRL_PORT1));
OALLog(L" CTRL_SMP = 0x%02x\r\n", (UINT8)INREG32(&pETH->CTRL_SMP));
OALLog(L" CTRL_MODE = 0x%02x\r\n", (UINT8)INREG32(&pETH->CTRL_MODE));
OALLog(L" CTRL_PAUSE = 0x%04x\r\n", (UINT16)INREG32(&pETH->CTRL_PAUSE));
OALLog(L" CTRL_PRIMAP_PORT0 = 0x%02x\r\n", (UINT8)INREG32(&pETH->CTRL_PRIMAP_PORT0));
OALLog(L" CTRL_PRIMAP_PORT1 = 0x%02x\r\n", (UINT8)INREG32(&pETH->CTRL_PRIMAP_PORT1));
OALLog(L" CTRL_PRIMAP_SMP = 0x%02x\r\n", (UINT8)INREG32(&pETH->CTRL_PRIMAP_SMP));
OALLog(L" CTRL_PRICTL_PORT0 = 0x%02x\r\n", (UINT8)INREG32(&pETH->CTRL_PRICTL_PORT0));
OALLog(L" CTRL_PRICTL_PORT1 = 0x%02x\r\n", (UINT8)INREG32(&pETH->CTRL_PRICTL_PORT1));
OALLog(L" CTRL_PRICTL_SMP = 0x%02x\r\n", (UINT8)INREG32(&pETH->CTRL_PRICTL_SMP));
OALLog(L" CTRL_PRIREG_PORT0 = 0x%08x\r\n", INREG32(&pETH->CTRL_PRIREG_PORT0));
OALLog(L" CTRL_PRIREG_PORT1 = 0x%08x\r\n", INREG32(&pETH->CTRL_PRIREG_PORT1));
OALLog(L" CTRL_VLAN = 0x%02x\r\n", (UINT8)INREG32(&pETH->CTRL_VLAN));
OALLog(L" CTRL_VLAN_PORT0 = 0x%08x\r\n", INREG32(&pETH->CTRL_VLAN_PORT0));
OALLog(L" CTRL_VLAN_PORT1 = 0x%08x\r\n", INREG32(&pETH->CTRL_VLAN_PORT1));
OALLog(L" CTRL_VLAN_SMP = 0x%08x\r\n", INREG32(&pETH->CTRL_VLAN_SMP));
OALLog(L" STAT_LINK = 0x%08x\r\n", INREG32(&pETH->STAT_LINK));
OALLog(L" STAT_LINKCHG = 0x%08x\r\n", INREG32(&pETH->STAT_LINKCHG));
OALLog(L" STAT_SPEED = 0x%08x\r\n", INREG32(&pETH->STAT_SPEED));
OALLog(L" STAT_DUPLEX = 0x%08x\r\n", INREG32(&pETH->STAT_DUPLEX));
OALLog(L" STAT_PAUSE = 0x%08x\r\n", INREG32(&pETH->STAT_PAUSE));
OALLog(L" STAT_SA_CHG = 0x%08x\r\n", INREG32(&pETH->STAT_SA_CHG));
OALLog(L" STAT_SA_LSW_PORT0 = 0x%08x\r\n", INREG32(&pETH->STAT_SA_LSW_PORT0));
OALLog(L" STAT_SA_MSW_PORT0 = 0x%08x\r\n", INREG32(&pETH->STAT_SA_MSW_PORT0));
OALLog(L" STAT_SA_LSW_PORT1 = 0x%08x\r\n", INREG32(&pETH->STAT_SA_LSW_PORT1));
OALLog(L" STAT_SA_MSW_PORT1 = 0x%08x\r\n", INREG32(&pETH->STAT_SA_MSW_PORT1));
OALLog(L" STAT_SA_LSW_SMP = 0x%08x\r\n", INREG32(&pETH->STAT_SA_LSW_SMP));
OALLog(L" STAT_SA_MSW_SMP = 0x%08x\r\n", INREG32(&pETH->STAT_SA_MSW_SMP));
OALLog(L" STAT_BIST = 0x%08x\r\n", INREG32(&pETH->STAT_BIST));
OALLog(L" MGMT_GLB = 0x%08x\r\n", INREG32(&pETH->MGMT_GLB));
OALLog(L" MGMT_CHIPID = 0x%08x\r\n", INREG32(&pETH->MGMT_CHIPID));
OALLog(L" MGMT_PORTID = 0x%08x\r\n", INREG32(&pETH->MGMT_PORTID));
OALLog(L" MGMT_RMON = 0x%08x\r\n", INREG32(&pETH->MGMT_RMON));
OALLog(L" MGMT_AGE = 0x%08x\r\n", INREG32(&pETH->MGMT_AGE));
OALLog(L" MGMT_MIRCAP = 0x%08x\r\n", INREG32(&pETH->MGMT_MIRCAP));
OALLog(L" MGMT_MIRIGR = 0x%08x\r\n", INREG32(&pETH->MGMT_MIRIGR));
OALLog(L" MGMT_MIRIGRDIV = 0x%08x\r\n", INREG32(&pETH->MGMT_MIRIGRDIV));
OALLog(L" MGMT_MIRIGRMAC_LSW = 0x%08x\r\n", INREG32(&pETH->MGMT_MIRIGRMAC_LSW));
OALLog(L" MGMT_MIRIGRMAC_MSW = 0x%08x\r\n", INREG32(&pETH->MGMT_MIRIGRMAC_MSW));
OALLog(L" MGMT_MIREGR = 0x%08x\r\n", INREG32(&pETH->MGMT_MIREGR));
OALLog(L" MGMT_MIREGRDIV = 0x%08x\r\n", INREG32(&pETH->MGMT_MIREGRDIV));
OALLog(L" MGMT_MIREGRMAC_LSW = 0x%08x\r\n", INREG32(&pETH->MGMT_MIREGRMAC_LSW));
OALLog(L" MGMT_MIREGRMAC_MSW = 0x%08x\r\n", INREG32(&pETH->MGMT_MIREGRMAC_MSW));
OALLog(L" MIBA_PORT = 0x%08x\r\n", INREG32(&pETH->MIBA_PORT));
OALLog(L" MIBA_HDRPTR = 0x%08x\r\n", INREG32(&pETH->MIBA_HDRPTR));
OALLog(L" MIBA_HDRLEN = 0x%08x\r\n", INREG32(&pETH->MIBA_HDRLEN));
OALLog(L" MIBA_DA_LSW = 0x%08x\r\n", INREG32(&pETH->MIBA_DA_LSW));
OALLog(L" MIBA_DA_MSW = 0x%08x\r\n", INREG32(&pETH->MIBA_DA_MSW));
OALLog(L" MIBA_SA_LSW = 0x%08x\r\n", INREG32(&pETH->MIBA_SA_LSW));
OALLog(L" MIBA_SA_MSW = 0x%08x\r\n", INREG32(&pETH->MIBA_SA_MSW));
OALLog(L" MIBA_TYPE = 0x%08x\r\n", INREG32(&pETH->MIBA_TYPE));
OALLog(L" MIBA_RATE = 0x%08x\r\n", INREG32(&pETH->MIBA_RATE));
OALLog(L" ARLC_GLB = 0x%08x\r\n", INREG32(&pETH->ARLC_GLB));
OALLog(L" ARLC_BPDU_LSW = 0x%08x\r\n", INREG32(&pETH->ARLC_BPDU_LSW));
OALLog(L" ARLC_BPDU_MSW = 0x%08x\r\n", INREG32(&pETH->ARLC_BPDU_MSW));
OALLog(L" ARLC_MPA1_LSW = 0x%08x\r\n", INREG32(&pETH->ARLC_MPA1_LSW));
OALLog(L" ARLC_MPA1_MSW = 0x%08x\r\n", INREG32(&pETH->ARLC_MPA1_MSW));
OALLog(L" ARLC_MPV1 = 0x%08x\r\n", INREG32(&pETH->ARLC_MPV1));
OALLog(L" ARLC_MPA2_LSW = 0x%08x\r\n", INREG32(&pETH->ARLC_MPA2_LSW));
OALLog(L" ARLC_MPA2_MSW = 0x%08x\r\n", INREG32(&pETH->ARLC_MPA2_MSW));
OALLog(L" ARLC_MPV2 = 0x%08x\r\n", INREG32(&pETH->ARLC_MPV2));
OALLog(L" ARLC_SECSP = 0x%08x\r\n", INREG32(&pETH->ARLC_SECSP));
OALLog(L" ARLC_SECDP = 0x%08x\r\n", INREG32(&pETH->ARLC_SECDP));
OALLog(L" PORT0_MII_CTRL = 0x%04x\r\n", INREG16(&pETH->PORT0_MII_CTRL));
OALLog(L" PORT0_MII_STS = 0x%04x\r\n", INREG16(&pETH->PORT0_MII_STS));
OALLog(L" PORT0_MII_PHYIDHIGH = 0x%04x\r\n", INREG16(&pETH->PORT0_MII_PHYIDHIGH));
OALLog(L" PORT0_MII_PHYIDLOW = 0x%04x\r\n", INREG16(&pETH->PORT0_MII_PHYIDLOW));
OALLog(L" PORT0_MII_ANEGAD = 0x%04x\r\n", INREG16(&pETH->PORT0_MII_ANEGAD));
OALLog(L" PORT0_MII_ANEGLP = 0x%04x\r\n", INREG16(&pETH->PORT0_MII_ANEGLP));
OALLog(L" PORT0_MII_ANEGEXP = 0x%04x\r\n", INREG16(&pETH->PORT0_MII_ANEGEXP));
OALLog(L" PORT0_MII_ANEGNEXT = 0x%04x\r\n", INREG16(&pETH->PORT0_MII_ANEGNEXT));
OALLog(L" PORT0_MII_ANEGLPNEXT = 0x%04x\r\n", INREG16(&pETH->PORT0_MII_ANEGLPNEXT));
OALLog(L" PORT0_MII_100BX = 0x%04x\r\n", INREG16(&pETH->PORT0_MII_100BX));
OALLog(L" PORT0_MII_100BXSTS = 0x%04x\r\n", INREG16(&pETH->PORT0_MII_100BXSTS));
OALLog(L" PORT0_MII_100BXERR = 0x%04x\r\n", INREG16(&pETH->PORT0_MII_100BXERR));
OALLog(L" PORT0_MII_100BXCS = 0x%04x\r\n", INREG16(&pETH->PORT0_MII_100BXCS));
OALLog(L" PORT0_MII_100BXDIS = 0x%04x\r\n", INREG16(&pETH->PORT0_MII_100BXDIS));
OALLog(L" PORT0_MII_RSVD1 = 0x%04x\r\n", INREG16(&pETH->PORT0_MII_RSVD1));
OALLog(L" PORT0_MII_RSVD4 = 0x%04x\r\n", INREG16(&pETH->PORT0_MII_RSVD4));
OALLog(L" PORT0_MII_PTEST = 0x%04x\r\n", INREG16(&pETH->PORT0_MII_PTEST));
OALLog(L" PORT0_MII_AUXCTRL = 0x%04x\r\n", INREG16(&pETH->PORT0_MII_AUXCTRL));
OALLog(L" PORT0_MII_AUXSTS = 0x%04x\r\n", INREG16(&pETH->PORT0_MII_AUXSTS));
OALLog(L" PORT0_MII_INT = 0x%04x\r\n", INREG16(&pETH->PORT0_MII_INT));
OALLog(L" PORT0_MII_AUXMODE2 = 0x%04x\r\n", INREG16(&pETH->PORT0_MII_AUXMODE2));
OALLog(L" PORT0_MII_10BTAUX = 0x%04x\r\n", INREG16(&pETH->PORT0_MII_10BTAUX));
OALLog(L" PORT0_MII_AUXMODE = 0x%04x\r\n", INREG16(&pETH->PORT0_MII_AUXMODE));
OALLog(L" PORT0_MII_AUXPHY = 0x%04x\r\n", INREG16(&pETH->PORT0_MII_AUXPHY));
OALLog(L" PORT0_MII_BRCMTEST = 0x%04x\r\n", INREG16(&pETH->PORT0_MII_BRCMTEST));
OALLog(L" PORT1_MII_CTRL = 0x%04x\r\n", INREG16(&pETH->PORT1_MII_CTRL));
OALLog(L" PORT1_MII_STS = 0x%04x\r\n", INREG16(&pETH->PORT1_MII_STS));
OALLog(L" PORT1_MII_PHYIDHIGH = 0x%04x\r\n", INREG16(&pETH->PORT1_MII_PHYIDHIGH));
OALLog(L" PORT1_MII_PHYIDLOW = 0x%04x\r\n", INREG16(&pETH->PORT1_MII_PHYIDLOW));
OALLog(L" PORT1_MII_ANEGAD = 0x%04x\r\n", INREG16(&pETH->PORT1_MII_ANEGAD));
OALLog(L" PORT1_MII_ANEGLP = 0x%04x\r\n", INREG16(&pETH->PORT1_MII_ANEGLP));
OALLog(L" PORT1_MII_ANEGEXP = 0x%04x\r\n", INREG16(&pETH->PORT1_MII_ANEGEXP));
OALLog(L" PORT1_MII_ANEGNEXT = 0x%04x\r\n", INREG16(&pETH->PORT1_MII_ANEGNEXT));
OALLog(L" PORT1_MII_ANEGLPNEXT = 0x%04x\r\n", INREG16(&pETH->PORT1_MII_ANEGLPNEXT));
OALLog(L" PORT1_MII_100BX = 0x%04x\r\n", INREG16(&pETH->PORT1_MII_100BX));
OALLog(L" PORT1_MII_100BXSTS = 0x%04x\r\n", INREG16(&pETH->PORT1_MII_100BXSTS));
OALLog(L" PORT1_MII_100BXERR = 0x%04x\r\n", INREG16(&pETH->PORT1_MII_100BXERR));
OALLog(L" PORT1_MII_100BXCS = 0x%04x\r\n", INREG16(&pETH->PORT1_MII_100BXCS));
OALLog(L" PORT1_MII_100BXDIS = 0x%04x\r\n", INREG16(&pETH->PORT1_MII_100BXDIS));
OALLog(L" PORT1_MII_RSVD1 = 0x%04x\r\n", INREG16(&pETH->PORT1_MII_RSVD1));
OALLog(L" PORT1_MII_RSVD4 = 0x%04x\r\n", INREG16(&pETH->PORT1_MII_RSVD4));
OALLog(L" PORT1_MII_PTEST = 0x%04x\r\n", INREG16(&pETH->PORT1_MII_PTEST));
OALLog(L" PORT1_MII_AUXCTRL = 0x%04x\r\n", INREG16(&pETH->PORT1_MII_AUXCTRL));
OALLog(L" PORT1_MII_AUXSTS = 0x%04x\r\n", INREG16(&pETH->PORT1_MII_AUXSTS));
OALLog(L" PORT1_MII_INT = 0x%04x\r\n", INREG16(&pETH->PORT1_MII_INT));
OALLog(L" PORT1_MII_AUXMODE2 = 0x%04x\r\n", INREG16(&pETH->PORT1_MII_AUXMODE2));
OALLog(L" PORT1_MII_10BTAUX = 0x%04x\r\n", INREG16(&pETH->PORT1_MII_10BTAUX));
OALLog(L" PORT1_MII_AUXMODE = 0x%04x\r\n", INREG16(&pETH->PORT1_MII_AUXMODE));
OALLog(L" PORT1_MII_AUXPHY = 0x%04x\r\n", INREG16(&pETH->PORT1_MII_AUXPHY));
OALLog(L" PORT1_MII_BRCMTEST = 0x%04x\r\n", INREG16(&pETH->PORT1_MII_BRCMTEST));
OALLog(L"===================================\r\n");
}
//------------------------------------------------------------------------------
VOID BCM11DumpETHALR()
{
BCM11_ETH_REGS *pETH = OALPAtoUA(BCM11_ETH_REGS_PA);
UINT32 address, i, lo, hi;
UINT8 mac[6];
OALLog(L"\r\n");
OALLog(L"========= BCM11xx ETH ALR =========\r\n");
for (i = 0; i < SSRAM_ARL_ENTRIES; i++) {
address = ((i & 0x03E0) << 3)|0x00E0|(i & 0x001F);
// put SSRAM into read mode
OUTREG32(&pETH->SSRAM_ADDR, SSRAM_READ);
// set SSRAM address
OUTREG32(&pETH->SSRAM_ADDR, SSRAM_READ|address);
// start read
OUTREG32(&pETH->SSRAM_ADDR, SSRAM_READ|SSRAM_START|address);
// wait for read done
while ((INREG32(&pETH->SSRAM_ADDR) & SSRAM_START) != 0);
// read data
lo = INREG32(&pETH->SSRAM_DATA_LSW);
hi = INREG32(&pETH->SSRAM_DATA_MSW);
// skip if entry isn't valid
if ((hi & (1 << 31)) == 0) continue;
mac[0] = RevertByte((UINT8)(hi >> 8));
mac[1] = RevertByte((UINT8)(hi >> 0));
mac[2] = RevertByte((UINT8)(lo >> 24));
mac[3] = RevertByte((UINT8)(lo >> 16));
mac[4] = RevertByte((UINT8)(lo >> 8));
mac[5] = RevertByte((UINT8)(lo >> 0));
OALLog(
L"%02x:%02x:%02x:%02x:%02x:%02x -> %d/%-2d (%s, %s, %s) %08x:%08x\r\n",
mac[0], mac[1], mac[2], mac[3], mac[4], mac[5],
((hi >> 20)&0xF), ((hi >> 16)&0xF),
((hi & (1 << 30)) != 0) ? L"static" : L"dynamic",
((hi & (1 << 29)) != 0) ? L"age" : L"no-age",
((hi & (1 << 28)) != 0) ? L"pri" : L"normal", hi, lo
);
}
OALLog(L"===================================\r\n");
}
//------------------------------------------------------------------------------
static UINT8 RevertByte(UINT8 b)
{
INT j;
UCHAR rb;
for (j = 0, rb = 0; j < 8; j++) {
rb <<= 1;
if ((b & 0x01) != 0) rb |= 0x01;
b >>= 1;
}
return rb;
}
//------------------------------------------------------------------------------
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