📄 tlb.s
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//
// Copyright (c) Microsoft Corporation. All rights reserved.
//
//
// Use of this source code is subject to the terms of the Microsoft end-user
// license agreement (EULA) under which you licensed this SOFTWARE PRODUCT.
// If you did not accept the terms of the EULA, you are not authorized to use
// this source code. For a copy of the EULA, please see the LICENSE.RTF on your
// install media.
//
#include <kxmips.h>
#include <nkintr.h>
#define KSEG0_BASE 0x80000000
//------------------------------------------------------------------------------
.text
.globl OEMTLBSize
.globl Au1InstallTLBHandler
OEMTLBSize:
.word 31
//------------------------------------------------------------------------------
//
// Function: OALClearTLB
//
// Clear all TLB entries. Because MIPS has unified TLB and there isn't simple
// way how to find TLB entry for address full TLB is cleared each time.
//
LEAF_ENTRY(OALClearTLB)
.set noreorder
.text
mfc0 t0, psr // Save current psr
mfc0 t1, entryhi // Save current asid
nop
andi t2, t0, 0xFFFE // Mask interrupts
mtc0 t2, psr // Disable interrupts
nop // fill delay slot
li t2, KSEG0_BASE // Unmapped address
lw t3, OEMTLBSize // (t3) = index & loop counter
mfc0 t4, wired // (t4) = loop limit
10: mtc0 zero, entrylo0 // Clear entrylo0 - Invalid entry
mtc0 zero, entrylo1 // Clear entrylo1 - Invalid entry
mtc0 t2, entryhi // Clear entryhi - Ivalid address
mtc0 t3, index // Set index
add t2, 0x2000
nop // Fill delay slot
tlbwi // Write entry (indexed)
nop
bne t3, t4, 10b // If not zero do next one
addu t3, -1 // Decrement index, loop counter
mtc0 t1, entryhi // Restore asid
mtc0 t0, psr // Restore psr
j ra
sync
.end OALClearTlb
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//
// Function: Au1InstallTLBHandler
//
// Install AU1 specific TLB miss handler. The TLB miss handler has
// some kind of hazard that requires flushing instruction pipeline.
//
LEAF_ENTRY(Au1InstallTLBHandler)
// (1) Only install it when we're not profiler build, for profiler build
// is jumping to TLBMissHandler already.
// (2) We're assuming that the 1st instruction of TLBMissHandler to be
// "mfc0 k0, badvaddr" and we will not install the handler if this is not
// the case (profiler build).
li t0, 0x401A4000 // (t0) = code-byte for 'mfc0 k0, badvaddr'
li t1, 0xa0000000 // (t1) = address of TLB exception vector (uncached)
lw t2, (t1) // (t2) = 1st instruction of TLB miss handler
bne t0, t2, Au1Done // do nothing if the 1st instruction is not 'mfc0 k0, badvaddr'
nop
// replace the handler with the code below
la t0, Au1TLBMissHandler
// copy 4 instructions
// (t0) = address of AU1 handler
// (t1) = address of the TLB exception vector
lw a0, (t0)
lw a1, 4(t0)
lw a2, 8(t0)
lw a3, 12(t0)
sw a0, (t1)
sw a1, 4(t1)
sw a2, 8(t1)
sw a3, 12(t1)
Au1Done:
j ra
nop
Au1TLBMissHandler:
la k0, TLBMissHandler // 2 DWORDS
j k0 // 1 DWORD
ssnop // 1 DWORD
.end Au1InstallTLBHandler
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