io.s

Windows CE 6.0 BSP for VOIPAC Board (PXA270) Version 2b.

//
// Copyright (c) Microsoft Corporation.  All rights reserved.
//
//
// Use of this source code is subject to the terms of the Microsoft end-user
// license agreement (EULA) under which you licensed this SOFTWARE PRODUCT.
// If you did not accept the terms of the EULA, you are not authorized to use
// this source code. For a copy of the EULA, please see the LICENSE.RTF on your
// install media.
//
#include "kxmips.h"

        .set    noreorder

//------------------------------------------------------------------------------
// UCHAR READ_PORT_UCHAR(UCHAR *pPort)

LEAF_ENTRY(READ_PORT_UCHAR)
ALTERNATE_ENTRY(READ_REGISTER_UCHAR)

        j       ra
        lbu     v0, 0(a0)
        .end
    
//------------------------------------------------------------------------------
// USHORT READ_PORT_USHORT(USHORT *pPort)

LEAF_ENTRY(READ_PORT_USHORT)
ALTERNATE_ENTRY(READ_REGISTER_USHORT)

        j       ra
        lhu     v0, 0(a0)
        .end

//------------------------------------------------------------------------------
// ULONG READ_PORT_ULONG(ULONG *pPort)

LEAF_ENTRY(READ_PORT_ULONG)
ALTERNATE_ENTRY(READ_REGISTER_ULONG)

        j       ra
        lw      v0, 0(a0)
        .end

//------------------------------------------------------------------------------
// VOID WRITE_PORT_UCHAR(UCHAR *pPort, UCHAR value)

LEAF_ENTRY(WRITE_PORT_UCHAR)
ALTERNATE_ENTRY(WRITE_REGISTER_UCHAR)

        sync
        sb      a1, 0(a0)
        j       ra
        sync
        .end

//------------------------------------------------------------------------------
// VOID WRITE_PORT_USHORT(USHORT *pPort, USHORT value)

LEAF_ENTRY(WRITE_PORT_USHORT)
ALTERNATE_ENTRY(WRITE_REGISTER_USHORT)

        sync
        sh      a1, 0(a0)
        j       ra
        sync
        .end

//------------------------------------------------------------------------------
// VOID WRITE_PORT_ULONG(ULONG *pPort, ULONG value)

LEAF_ENTRY(WRITE_PORT_ULONG)
ALTERNATE_ENTRY(WRITE_REGISTER_ULONG)

        sync
        sw      a1, 0(a0)
        j       ra
        sync
        .end

//------------------------------------------------------------------------------
// VOID READ_PORT_BUFFER_UCHAR(UCHAR *pPort, UCHAR *pBuffer, ULONG count)

LEAF_ENTRY(READ_PORT_BUFFER_UCHAR)
ALTERNATE_ENTRY(READ_REGISTER_BUFFER_UCHAR)

10:     beqz    a2, 20f
        nop
        lbu     t0, 0(a0)
        sb      t0, 0(a1)
        addu    a1, 1
        j       10b
        addu    a2, -1
20:     j       ra
        nop
        .end

//------------------------------------------------------------------------------
// VOID READ_PORT_BUFFER_USHORT(USHORT *pPort, USHORT *pBuffer, ULONG count)

LEAF_ENTRY(READ_PORT_BUFFER_USHORT)
ALTERNATE_ENTRY(READ_REGISTER_BUFFER_USHORT)

10:     beqz    a2, 20f
        nop
        lhu     t0, 0(a0)
        sh      t0, 0(a1)
        addu    a1, 2
        j       10b
        addu    a2, -1
20:     j       ra
        nop
        .end

//------------------------------------------------------------------------------
// VOID READ_PORT_BUFFER_ULONG(ULONG *pPort, ULONG *pBuffer, ULONG count)

LEAF_ENTRY(READ_PORT_BUFFER_ULONG)
ALTERNATE_ENTRY(READ_REGISTER_BUFFER_ULONG)

10:     beqz    a2, 20f
        nop
        lw      t0, 0(a0)
        sw      t0, 0(a1)
        addu    a1, 4
        j       10b
        addu    a2, -1
20:     j       ra
        nop
        .end

//------------------------------------------------------------------------------
// VOID WRITE_PORT_BUFFER_UCHAR(UCHAR *pPort, UCHAR *pBuffer, ULONG count)

LEAF_ENTRY(WRITE_PORT_BUFFER_UCHAR)
ALTERNATE_ENTRY(WRITE_REGISTER_BUFFER_UCHAR)

10:     beqz    a2, 20f
        sync
        lbu     t0, 0(a1)
        sb      t0, 0(a0)
        addu    a1, 1
        j       10b
        addu    a2, -1
20:     j       ra
        sync
        .end

//------------------------------------------------------------------------------
// VOID WRITE_PORT_BUFFER_USHORT(USHORT *pPort, USHORT *pBuffer, ULONG count)

LEAF_ENTRY(WRITE_PORT_BUFFER_USHORT)
ALTERNATE_ENTRY(WRITE_REGISTER_BUFFER_USHORT)

10:     beqz    a2, 20f
        sync
        lhu     t0, 0(a1)
        sh      t0, 0(a0)
        addu    a1, 2
        j       10b
        addu    a2, -1
20:     j       ra
        sync
        .end

//------------------------------------------------------------------------------
// VOID WRITE_PORT_BUFFER_ULONG(ULONG *pPort, ULONG *pBuffer, ULONG count)

LEAF_ENTRY(WRITE_PORT_BUFFER_ULONG)
ALTERNATE_ENTRY(WRITE_REGISTER_BUFFER_ULONG)

10:     beqz    a2, 20f
        sync
        lw      t0, 0(a1)
        sw      t0, 0(a0)
        addu    a1, 4
        j       10b
        addu    a2, -1
20:     j       ra
        sync
        .end

//------------------------------------------------------------------------------