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//
// Copyright (c) Microsoft Corporation. All rights reserved.
//
//
// Use of this source code is subject to the terms of the Microsoft end-user
// license agreement (EULA) under which you licensed this SOFTWARE PRODUCT.
// If you did not accept the terms of the EULA, you are not authorized to use
// this source code. For a copy of the EULA, please see the LICENSE.RTF on your
// install media.
//
// Copyright (c) 1998 BSQUARE Corporation. All rights reserved.
//
#include <kxmips.h>
#include <nkintr.h>
#define __MIPS_ASSEMBLER
#include <au1_base_regs.h>
#include <au1_sys.h>
#include <au1_mem.h>
//------------------------------------------------------------------------------
#define KSEG0_BASE 0x80000000
#define KSEG1_BASE 0xA0000000
//------------------------------------------------------------------------------
.data
.align 4
regSave:
.space 0x0100
tlbSave:
.space 32*16
//------------------------------------------------------------------------------
.text
//------------------------------------------------------------------------------
//
// Function: OALCPUPowerOff
//
// This function save CPU state and move SoC to power off mode.
//
LEAF_ENTRY(OALCPUPowerOff)
.set noreorder
.set noat
la a0, regSave
// Save CPU registers
sw v1, 0x00(a0)
sw t0, 0x04(a0)
sw t1, 0x08(a0)
sw t2, 0x0C(a0)
sw t3, 0x10(a0)
sw t4, 0x14(a0)
sw t5, 0x18(a0)
sw t6, 0x1C(a0)
sw t7, 0x20(a0)
sw s0, 0x24(a0)
sw s1, 0x28(a0)
sw s2, 0x2C(a0)
sw s3, 0x30(a0)
sw s4, 0x34(a0)
sw s5, 0x38(a0)
sw s6, 0x3C(a0)
sw s7, 0x40(a0)
sw t8, 0x44(a0)
sw t9, 0x48(a0)
sw k0, 0x4C(a0)
sw k1, 0x50(a0)
sw gp, 0x54(a0)
sw sp, 0x58(a0)
sw s8, 0x5C(a0)
sw ra, 0x60(a0)
mfhi t0
nop
sw t0, 0x64(a0)
mflo t1
nop
sw t1, 0x68(a0)
// Save CP0 registers
mfc0 a1, index
sw a1, 0x6C(a0)
mfc0 a1, random
sw a1, 0x70(a0)
mfc0 a1, entrylo0
sw a1, 0x74(a0)
mfc0 a1, entrylo1
sw a1, 0x78(a0)
mfc0 a1, context
sw a1, 0x7C(a0)
mfc0 a1, pagemask
sw a1, 0x80(a0)
mfc0 a1, wired
sw a1, 0x84(a0)
mfc0 a1, count
sw a1, 0x88(a0)
mfc0 a1, entryhi
sw a1, 0x8C(a0)
mfc0 a1, compare
sw a1, 0x90(a0)
mfc0 a1, psr
sw a1, 0x94(a0)
mfc0 a1, cause
sw a1, 0x98(a0)
mfc0 a1, epc
sw a1, 0x9C(a0)
mfc0 a1, config
sw a1, 0xA0(a0)
mfc0 a1, lladdr
sw a1, 0xA4(a0)
mfc0 a1, watchlo
sw a1, 0xA8(a0)
mfc0 a1, $20 // xcontext
sw a1, 0xAC(a0)
mfc0 a1, $26 // perr
sw a1, 0xB0(a0)
mfc0 a1, taglo
sw a1, 0xB4(a0)
mfc0 a1, taghi
sw a1, 0xB8(a0)
mfc0 a1, errorepc
sw a1, 0xBC(a0)
// Save TLB
la v0, tlbSave
move a1, zero
li a2, 31
10: mtc0 a1, index
nop
nop
tlbr
nop
nop
nop
addu a1, 1
mfc0 t0, entrylo0
mfc0 t1, entrylo1
mfc0 t2, entryhi
mfc0 t3, pagemask
sw t0, 0x00(v0)
sw t1, 0x04(v0)
sw t2, 0x08(v0)
sw t3, 0x0C(v0)
bne a1, a2, 10b
addu v0, 0x10
// Invalidate data cache
li t0, (16*1024)
li t1, 32
li t2, KSEG0_BASE
addu t3, t0, t2
20: cache 1, 0(t2)
addu t2, t1
bne t2, t3, 20b
nop
// Prefech instructions into the cache
la t1, 30f
cache 0x14, 0x00(t1)
cache 0x14, 0x20(t1)
cache 0x14, 0x40(t1)
cache 0x14, 0x60(t1)
cache 0x14, 0x80(t1)
cache 0x14, 0xa0(t1)
30:
// Put DRAM to autorefresh mode
li t1, AU1_MEM_REGS_PA|KSEG1_BASE
sw zero, AU1_MEM_SDPRECMD_REGS_OA(t1)
sw zero, AU1_MEM_SDAUTOREF_REGS_OA(t1)
sw zero, AU1_MEM_SDSLEEP_REGS_OA(t1)
sync
// Write to sleep_power register
li t0, AU1_SYS_REGS_PA|KSEG1_BASE
li t1, 1
sw t1, AU1_SYS_SLPPWR_REGS_OA(t0)
sync
// So let go sleep
nop
li t1, 1
sw t1, AU1_SYS_SLEEP_REGS_OA(t0)
sync
nop
nop
nop
nop
40: j 40b
nop
.set reorder
.set at
.end OALCPUPowerOff
//------------------------------------------------------------------------------
//
// Function: OALCPUPoweOn
//
// This function restore CPU state
//
LEAF_ENTRY(OALCPUPowerOn)
.set noreorder
.set noat
// Restore TLB
la v0, tlbSave
move a1, zero
li a2, 31
10: lw t0, 0x00(v0)
lw t1, 0x04(v0)
lw t2, 0x08(v0)
lw t3, 0x0C(v0)
mtc0 t0, entrylo0
mtc0 t1, entrylo1
mtc0 t2, entryhi
mtc0 t3, pagemask
mtc0 a1, index
nop
addu a1, 1
tlbwi
bne a1, a2, 10b
addu v0, 0x10
la a0, regSave
// Restore CP0
lw a1, 0x6C(a0)
mtc0 a1, index
lw a1, 0x70(a0)
mtc0 a1, random
lw a1, 0x74(a0)
mtc0 a1, entrylo0
lw a1, 0x78(a0)
mtc0 a1, entrylo1
lw a1, 0x7C(a0)
mtc0 a1, context
lw a1, 0x80(a0)
mtc0 a1, pagemask
lw a1, 0x84(a0)
mtc0 a1, wired
lw a1, 0x88(a0)
mtc0 a1, count
lw a1, 0x8C(a0)
mtc0 a1, entryhi
lw a1, 0x90(a0)
mtc0 a1, compare
lw a1, 0x98(a0)
mtc0 a1, cause
lw a1, 0x9C(a0)
mtc0 a1, epc
lw a1, 0xA0(a0)
mtc0 a1, config
lw a1, 0xA4(a0)
mtc0 a1, lladdr
lw a1, 0xA8(a0)
mtc0 a1, watchlo
lw a1, 0xAC(a0)
mtc0 a1, $20 // xcontext
lw a1, 0xB0(a0)
mtc0 a1, $26 // perr
lw a1, 0xB4(a0)
mtc0 a1, taglo
lw a1, 0xB8(a0)
mtc0 a1, taghi
lw a1, 0xBC(a0)
mtc0 a1, errorepc
// Restore psr
lw a1, 0x94(a0)
mtc0 a1, psr
// Restore CPU registers
lw a1, 0x64(a0)
lw a2, 0x68(a0)
mthi a1
lw v1, 0x00(a0)
mtlo a2
lw t0, 0x04(a0)
lw t1, 0x08(a0)
lw t2, 0x0C(a0)
lw t3, 0x10(a0)
lw t4, 0x14(a0)
lw t5, 0x18(a0)
lw t6, 0x1C(a0)
lw t7, 0x20(a0)
lw s0, 0x24(a0)
lw s1, 0x28(a0)
lw s2, 0x2C(a0)
lw s3, 0x30(a0)
lw s4, 0x34(a0)
lw s5, 0x38(a0)
lw s6, 0x3C(a0)
lw s7, 0x40(a0)
lw t8, 0x44(a0)
lw t9, 0x48(a0)
lw k0, 0x4C(a0)
lw k1, 0x50(a0)
lw gp, 0x54(a0)
lw sp, 0x58(a0)
lw s8, 0x5C(a0)
lw ra, 0x60(a0)
nop
nop
// Return back to OEMPowerOff
j ra
nop
.set reorder
.set at
.end OAKCPUPowerOn
//------------------------------------------------------------------------------
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