msr.h

Windows CE 6.0 BSP for VOIPAC Board (PXA270) Version 2b.

//  1            6 5 4   2 1     6 5            0 9 8   6 5     0
// |--------------|-|-----|-------|--------------|-|-----|-------|
//     RESERVED    P  CC1    ES1      RESERVED    P  CC0    ES0
//                 C                              C
//                 1                              0
//
// PC0 and PC1 - Pin control flags: Selects the function of the external
//               performance-monitoring counter pin (PM0/BP0 and PM1/BP1).
//               Setting one of these flags to 1 causes the processor to assert
//               its associated pin when the counter has overflowed; setting the
//               flag to 0 causes the pin to be asserted when the counter has
//               been incremented.  These flags permit the pins to be 
//               individually programmed to indicate the overflow or incremented
//               condition.  Note that the external signaling of the event on
//               the pins will lag the internal event by a few clocks as the
//               signals are latched and buffered.
// CC0 and CC1 - Counter control fields: Controls the operation of the counter.
//               (See CESR_CC_* flags above.)
// ES0 and ES1 - Event select fields: Selects (by entering an event code in the
//               field) up to two events to be monitored.
//               (See CESR_PERFORMANCE_EVENT values.)
//
#define CESR_PinCtl1Shift                   25
#define CESR_PinCtl1Mask                    ((DWORD)1 << CESR_PinCtl1Shift)
#define CESR_CtrCtl1Shift                   22
#define CESR_EvtSel1Shift                   16
#define CESR_PinCtl0Shift                   9
#define CESR_PinCtl0Mask                    ((DWORD)1 << CESR_PinCtl0Shift)
#define CESR_CtrCtl0Shift                   6
#define MAKE_CESR_VALUE(fCountClocks0, wES0, fCountClocks1, wES1)              \
    (  ((DWORD)(((fCountClocks1) ? CESR_CC_COUNT_CLOCKS : 0)                   \
                | CESR_CC_ENABLE_CPL3                                          \
                | CESR_CC_ENABLE_CPL012) << CESR_CtrCtl1Shift)                 \
     | ((DWORD)((wES1) & 0x3F) << CESR_EvtSel1Shift)                           \
     | ((DWORD)(((fCountClocks0) ? CESR_CC_COUNT_CLOCKS : 0)                   \
                | CESR_CC_ENABLE_CPL3                                          \
                | CESR_CC_ENABLE_CPL012) << CESR_CtrCtl0Shift)                 \
     | ((DWORD)((wES0) & 0x3F)))


//
// The 40-bit CTR0 and CTR1 registers are just numbers.
//


//------------------------------------------------------------------------------
// PERFORMANCE-MONITORING DEFINITIONS for P6-family processors
//------------------------------------------------------------------------------

//
// Contents of the 32-bit PerfEvtSel0 and PerfEvtSel1 registers (P6 only):
//
//  3             2 2 2 2 2 1 1 1 1 1          
//  1             4 3 2 1 0 9 8 7 6 5          8 7              0
// |---------------|-|-|-|-|-|-|-|-|------------|----------------|
//   COUNTER MASK   I E   I P E O U  UNIT MASK     EVENT SELECT
//                  N N   N C   S S              
//                  V     T       R
//
// COUNTER MASK - When nonzero, the processor compares this mask to the number
//                of events counted during a single cycle.  If the event count
//                is greater than or equal to this mask, the counter is
//                incremented by one.  Otherwise the counter is not incremented.
//                This mask can be used to count events only if multiple
//                occurrences happen per clock (for example, two or more
//                instructions retired per clock).  If the counter-mask field is
//                0, then the counter is incremented each cycle by the number of
//                events that occurred that cycle.
// INV          - Invert counter mask: Inverts the result of the counter-mask
//                comparison when set, so that both greater than and less than
//                comparisons can be made.
// EN           - Enable Counters (PerfEvtSel0 ONLY): When set, performance
//                counting is enabled in both performance-monitoring counters;
//                when clear, both counters are disabled.
// RES          - RESERVED
// INT          - APIC interrupt enable: When set the processor generates an 
//                exception through its local APIC on counter overflow.
// PC           - Pin control: When set, the processor toggles the PMi pins and
//                increments the counter when performance-monitoring events
//                occur; when clear, the processor toggles the PMi pins when the
//                counter overflows.
// E            - Edge detect: Enables (when set) edge detection of events.  The
//                processor counts the number of deasserted to asserted 
//                transitions of any condition that can be expressed by the
//                other fields.  The mechanism is limited in that it does not
//                permit back-to-back assertions to be distinguished.  This
//                mechanism allows software to measure not only the fraction of
//                time spent in a particular state, but also the average length
//                of time spent in such a state (for example, the time spent
//                waiting for an interrupt to be serviced).
// OS           - Operating system mode: Specifies that events are counted only
//                when the processor is operating at privilege level 0.  This
//                flag can be used in conjunction with the USR flag.
// USR          - User mode: Specifies that events are counted only when the
//                processor is operating at privilege levels 1, 2 or 3.  This
//                flag can be used in conjunction with the OS flag.
// UNIT MASK    - Further qualifies the event selected in the event select 
//                field.  For example, for some cache events, the mask is used
//                as a MESI-protocol qualifier of cache states.
// EVENT SELECT - Selects the event to be monitored.
//
#define PerfEvtSel_CounterMaskShift         24
#define PerfEvtSel_InvertMask               ((DWORD)1 << 23)
#define PerfEvtSel_EnableMask               ((DWORD)1 << 22)
#define PerfEvtSel_InterruptEnableMask      ((DWORD)1 << 20)
#define PerfEvtSel_PinControlMask           ((DWORD)1 << 19)
#define PerfEvtSel_EdgeDetectMask           ((DWORD)1 << 18)
#define PerfEvtSel_OSModeMask               ((DWORD)1 << 17)
#define PerfEvtSel_UserModeMask             ((DWORD)1 << 16)
#define PerfEvtSel_UnitMaskShift            8
#define MAKE_PERFEVTSEL_VALUE(fInterrupt, wUnitMask, wEventType)               \
    (((fInterrupt) ? PerfEvtSel_InterruptEnableMask : 0)                       \
     | PerfEvtSel_OSModeMask | PerfEvtSel_UserModeMask                         \
     | ((DWORD)((wUnitMask) & 0xFF) << PerfEvtSel_UnitMaskShift)               \
     | ((DWORD)((wEventType) & 0xFF)))

//
// The 40-bit PerfCtr0 and PerfCtr1 registers are just numbers.
//


// Enable entry point for performance counter library
#ifdef ENABLE_PERFCTR
extern VOID CPUPerfCounterInit();
extern HRESULT CPUPerfCounterIoctl(LPVOID lpInBuf, DWORD nInBufSize,
                                   LPVOID lpOutBuf, DWORD nOutBufSize,
                                   LPDWORD lpBytesReturned);
extern VOID CPUPerfCounterOverflowHandler(unsigned int ra);
#else
#define CPUPerfCounterInit()                ((VOID)0)
#define CPUPerfCounterIoctl(lpInBuf, nInBufSize, lpOutBuf, nOutBufSize, lpBytesReturned) \
    ((HRESULT)ERROR_NOT_SUPPORTED)
#define CPUPerfCounterOverflowHandler()     ((VOID)0)
#endif // ENABLE_PERFCTR


//------------------------------------------------------------------------------
// MSR DEFINITIONS
//------------------------------------------------------------------------------

// Addresses of MTRR and PAT registers, accessed via RDMSR and WRMSR instructions
#define MSRAddr_MTRRcap                     (0x000000FE)
#define MSRAddr_MTRRphysBase0               (0x00000200)  // PhysBaseN is Base0 + 2*N
#define MSRAddr_MTRRphysMask0               (0x00000201)  // PhysMaskN is Mask0 + 2*N
#define MSRAddr_MTRRdefType                 (0x000002FF)
#define MSRAddr_PAT                         (0x00000277)

// Address of Time Stamp Counter, accessed via RDMSR, WRMSR and RDTSC
#define MSRAddr_TSC                         (0x00000010)

// Addresses of Performance Counter registers for P5-family processors,
// accessed via RDMSR, WRMSR and RDPMC
#define MSRAddr_CESR                        (0x00000011)
#define MSRAddr_CTR0                        (0x00000012)
#define MSRAddr_CTR1                        (0x00000013)

// Addresses of Performance Counter registers for P6-family processors,
// accessed via RDMSR, WRMSR and RDPMC
#define MSRAddr_PerfCtr0                    (0x000000C1)
#define MSRAddr_PerfCtr1                    (0x000000C2)
#define MSRAddr_PerfEvtSel0                 (0x00000186)
#define MSRAddr_PerfEvtSel1                 (0x00000187)


extern BOOL NKwrmsr(
    DWORD dwAddr,       // Address of MSR being written
    DWORD dwValHigh,    // Upper 32 bits of value being written
    DWORD dwValLow      // Lower 32 bits of value being written
    );
extern BOOL NKrdmsr(
    DWORD dwAddr,       // Address of MSR being read
    DWORD *lpdwValHigh, // Receives upper 32 bits of value, can be NULL
    DWORD *lpdwValLow   // Receives lower 32 bits of value, can be NULL
    );


#endif // _MSR_H