msr.h

Windows CE 6.0 BSP for VOIPAC Board (PXA270) Version 2b.

//
// Copyright (c) Microsoft Corporation.  All rights reserved.
//
//
// Use of this source code is subject to the terms of the Microsoft end-user
// license agreement (EULA) under which you licensed this SOFTWARE PRODUCT.
// If you did not accept the terms of the EULA, you are not authorized to use
// this source code. For a copy of the EULA, please see the LICENSE.RTF on your
// install media.
//

#ifndef _MSR_H
#define _MSR_H


//
// Definitions required for working with x86 Model-Specific Registers
//


//------------------------------------------------------------------------------
// CPUID DEFINITIONS
//------------------------------------------------------------------------------

// IdentifyCpu returns the processor feature flags returned by the CPUID instruction
extern DWORD IdentifyCpu();

// See CPUID_ flags in public\common\oak\inc\pkfuncs.h

// The different parts of the CPU Signature
#define CPUID_MODEL(dwProcID)   (((dwProcID) >> 4) & 0xF)
#define CPUID_FAMILY(dwProcID)  (((dwProcID) >> 8) & 0xF)


//------------------------------------------------------------------------------
// PAT DEFINITIONS
//------------------------------------------------------------------------------

//
// PAT Entry Masks
//
#define PAT_Entry0Mask                      (0x0000000F)
#define PAT_Entry1Mask                      (0x00000F00)
#define PAT_Entry2Mask                      (0x000F0000)
#define PAT_Entry3Mask                      (0x0F000000)


//
// PAT Memory Types
//
// Cannot be used together
#define PAT_TypeUncacheable                 0
#define PAT_TypeWriteCombining              1
#define PAT_TypeWriteThrough                4
#define PAT_TypeWriteProtected              5
#define PAT_TypeWriteBack                   6
#define PAT_TypeUncachedOverrideable        7  // Can be overridden by WC in the MTRRs


//
// PAGE TABLE DEFINITIONS
//

// Three page table flags index into the PAT
#define x86_WRITE_THRU_MASK     0x00000008
#define x86_CACHE_MASK          0x00000010
#define x86_PAT_MASK            0x00000080

#define x86_PAT_INDEX0          (x86_PAT_MASK | 0             | 0)
#define x86_PAT_INDEX1          (x86_PAT_MASK | 0             | x86_WRITE_THRU_MASK)
#define x86_PAT_INDEX2          (x86_PAT_MASK | x86_CACHE_MASK | 0)
#define x86_PAT_INDEX3          (x86_PAT_MASK | x86_CACHE_MASK | x86_WRITE_THRU_MASK)
#define x86_PAT_INDEX_MASK      (x86_PAT_MASK | x86_CACHE_MASK | x86_WRITE_THRU_MASK)



//------------------------------------------------------------------------------
// MTRR DEFINITIONS
//------------------------------------------------------------------------------

//
// MTRR Memory Types
//
// Cannot be used together
#define MTRR_TypeUncacheable                0
#define MTRR_TypeWriteCombining             1
#define MTRR_TypeWriteThrough               4
#define MTRR_TypeWriteProtected             5
#define MTRR_TypeWriteBack                  6


//
// Contents of the 64-bit MTRRcap register if EAX=1
//
//  6                                    1 1
//  3                                    1 0 9 8 7              0
// |--------------------------------------|-|-|-|----------------|
//                RESERVED                 W   F      VCNT
//                                         C   X
//
// WC   - Write-combining memory type supported
// FX   - Fixed range registers supported
// VCNT - Number of variable range registers
//
#define MTRRcap_WriteCombineMask            ((DWORD)1 << 10)
#define MTRRcap_FixedRangeMask              ((DWORD)1 << 8)
#define MTRRcap_VarRangeRegisterCountMask   (((DWORD)1 << 8) - 1)


//
// Contents of the 64-bit MTRRdefType register:
//
//  6                                  1 1 1
//  3                                  2 1 0 9 8 7              0
// |------------------------------------|-|-|---|----------------|
//                RESERVED               E F RES      TYPE
//                                         E    
//
// E    - MTRR enable/disable
// FE   - Fixed-range MTRRs enable/disable
// RES  - RESERVED
// TYPE - Default memory type
//
#define MTRRdefType_EnableMask              ((DWORD)1 << 11)
#define MTRRdefType_FixedRangeEnableMask    ((DWORD)1 << 10)
#define MTRRdefType_DefaultTypeMask         (((DWORD)1 << 8) - 1)


//
// Contents of a 64-bit MTRRphysBase register:
//
//  6                  3 3             1 1  
//  3                  6 5             2 1     8 7              0
// |--------------------|---------------|-------|----------------|
//        RESERVED          PhysBase     RESERVD      TYPE
//                                              
//
// PhysBase - Base address of range, 4kB-aligned sign-extended
// TYPE     - Memory type of range
//
// On CE no address can exceed 32 bits so we can cut the base off there
#define MTRRphysBase_PhysBaseMask           (~(((DWORD)1 << 12) - 1))
#define MTRRphysBase_TypeMask               (((DWORD)1 << 8) - 1)


//
// Contents of a 64-bit MTRRphysMask register:
//
//  6                  3 3             1 1 1
//  3                  6 5             2 1 0                    0
// |--------------------|---------------|-|----------------------|
//        RESERVED          PhysMask     V        RESERVED
//                                              
//
// PhysMask - 24-bit mask that determines the range of the region being mapped,
//            according to tthe relationship:
//                Address_Within_Range AND PhysMask = PhysBase AND PhysMask
// V        - Valid, enables the register pair when set
//
// On CE no address can exceed 32 bits so we can cut the mask off there
#define MTRRphysMask_PhysMaskMask           (~(((DWORD)1 << 12) - 1))
#define MTRRphysMask_ValidMask              ((DWORD)1 << 11)



//------------------------------------------------------------------------------
// PERFORMANCE-MONITORING DEFINITIONS for P5-family processors
//------------------------------------------------------------------------------

// CESR Counter Control flags (bitmask together):
#define CESR_CC_COUNT_CLOCKS   0x4  // Set to count clocks (duration); clear to
                                    // count events
#define CESR_CC_ENABLE_CPL3    0x2  // Set to enable counting while CPL=3
#define CESR_CC_ENABLE_CPL012  0x1  // Set to enable counting while CPL=0, 1 or 2

//
// Contents of the 32-bit Control and Event Select Register (CESR) (P5 only):
//
//  3            2 2 2   2 2     1 1            1