intr.c

Windows CE 6.0 BSP for VOIPAC Board (PXA270) Version 2b.

            CLRREG32(&g_pIntcL2BRegs->MIR, 1 << (irq - 64));
        } else if (irq < IRQ_GPIO_32) {
            CLRREG32(&g_pIntcL1Regs->MIR, 1 << IRQ_GPIO1);
            CLRREG32(&g_pGPIO1Regs->INTMASK, 1 << (irq - 96));
        } else if (irq < IRQ_GPIO_64) {
            CLRREG32(&g_pIntcL1Regs->MIR, 1 << IRQ_GPIO2);
            CLRREG32(&g_pGPIO2Regs->INTMASK, 1 << (irq - IRQ_GPIO_32));
        } else if (irq < IRQ_GPIO_96) {
            CLRREG32(&g_pIntcL1Regs->MIR, 1 << IRQ_GPIO3);
            CLRREG32(&g_pGPIO3Regs->INTMASK, 1 << (irq - IRQ_GPIO_64));
        } else if (irq < IRQ_GPIO_128) {
            CLRREG32(&g_pIntcL2ARegs->MIR, 1 << (IRQ_GPIO4 - 32));
            CLRREG32(&g_pGPIO4Regs->INTMASK, 1 << (irq - IRQ_GPIO_96));
        } else if (irq < IRQ_GPIO_160) {
            CLRREG32(&g_pIntcL1Regs->MIR, 1 << IRQ_GPIO5);
            CLRREG32(&g_pGPIO5Regs->INTMASK, 1 << (irq - IRQ_GPIO_128));
        } else if (irq < OMAP730_IRQ_MAXIMUM) {
            CLRREG32(&g_pIntcL1Regs->MIR, 1 << IRQ_GPIO6);
            CLRREG32(&g_pGPIO6Regs->INTMASK, 1 << (irq - IRQ_GPIO_160));
        } else if (irq != OAL_INTR_IRQ_UNDEFINED) {
            rc = FALSE;
        }

    }

    OALMSG(OAL_INTR&&OAL_VERBOSE, (L"-OALIntrEnableIrqs(rc = %d)\r\n", rc));
    return rc;
}

//------------------------------------------------------------------------------
//
//  Function:  OALIntrDisableIrqs
//
VOID OALIntrDisableIrqs(UINT32 count, const UINT32 *pIrqs)
{
    UINT32 irq, i;

    OALMSG(OAL_INTR&&OAL_FUNC, (
        L"+OALIntrDisableIrqs(%d, 0x%08x)\r\n", count, pIrqs
    ));

    for (i = 0; i < count; i++) {
        irq = pIrqs[i];
        if (irq < 32) {
            SETREG32(&g_pIntcL1Regs->MIR, 1 << irq);
        } else if (irq < 64) {
            SETREG32(&g_pIntcL2ARegs->MIR, 1 << (irq - 32));
        } else if (irq < 96) {
            SETREG32(&g_pIntcL2BRegs->MIR, 1 << (irq - 64));
        } else if (irq < IRQ_GPIO_32) {
            SETREG32(&g_pGPIO1Regs->INTMASK, 1 << (irq - 96));
        } else if (irq < IRQ_GPIO_64) {
            SETREG32(&g_pGPIO2Regs->INTMASK, 1 << (irq - IRQ_GPIO_32));
        } else if (irq < IRQ_GPIO_96) {
            SETREG32(&g_pGPIO3Regs->INTMASK, 1 << (irq - IRQ_GPIO_64));
        } else if (irq < IRQ_GPIO_128) {
            SETREG32(&g_pGPIO4Regs->INTMASK, 1 << (irq - IRQ_GPIO_96));
        } else if (irq < IRQ_GPIO_160) {
            SETREG32(&g_pGPIO5Regs->INTMASK, 1 << (irq - IRQ_GPIO_128));
        } else if (irq < OMAP730_IRQ_MAXIMUM) {
            SETREG32(&g_pGPIO6Regs->INTMASK, 1 << (irq - IRQ_GPIO_160));
        }
    }
    OALMSG(OAL_INTR&&OAL_FUNC, (L"-OALIntrDisableIrqs\r\n"));
}

//------------------------------------------------------------------------------
//
//  Function:  OALIntrDoneIrqs
//
VOID OALIntrDoneIrqs(UINT32 count, const UINT32 *pIrqs)
{
    UINT32 irq, i;


    OALMSG(OAL_INTR&&OAL_VERBOSE, (
        L"+OALIntrDoneIrqs(%d, 0x%08x)\r\n", count, pIrqs
    ));

    for (i = 0; i < count; i++) {
        irq = pIrqs[i];
        if (irq < 32) {
            CLRREG32(&g_pIntcL1Regs->MIR, 1 << irq);
        } else if (irq < 64) {
            CLRREG32(&g_pIntcL2ARegs->MIR, 1 << (irq - 32));
        } else if (irq < 96) {
            CLRREG32(&g_pIntcL2BRegs->MIR, 1 << (irq - 64));
        } else if (irq < IRQ_GPIO_32) {
            CLRREG32(&g_pGPIO1Regs->INTMASK, 1 << (irq - 96));
        } else if (irq < IRQ_GPIO_64) {
            CLRREG32(&g_pGPIO2Regs->INTMASK, 1 << (irq - IRQ_GPIO_32));
        } else if (irq < IRQ_GPIO_96) {
            CLRREG32(&g_pGPIO3Regs->INTMASK, 1 << (irq - IRQ_GPIO_64));
        } else if (irq < IRQ_GPIO_128) {
            CLRREG32(&g_pGPIO4Regs->INTMASK, 1 << (irq - IRQ_GPIO_96));
        } else if (irq < IRQ_GPIO_160) {
            CLRREG32(&g_pGPIO5Regs->INTMASK, 1 << (irq - IRQ_GPIO_128));
        } else if (irq < OMAP730_IRQ_MAXIMUM) {
            CLRREG32(&g_pGPIO6Regs->INTMASK, 1 << (irq - IRQ_GPIO_160));
        }
    }
    OALMSG(OAL_INTR&&OAL_VERBOSE, (L"-OALIntrDoneIrq\r\n"));
}

//------------------------------------------------------------------------------
//
//  Function:  OEMInterruptHandler
//
//  This is interrupt handler implementation.
//
UINT32 OEMInterruptHandler()
{
    UINT32 irq = OAL_INTR_IRQ_UNDEFINED;
    UINT32 sysIntr = SYSINTR_NOP;
    UINT32 data, mask;
    OMAP730_GPIO_REGS *pGPIORegs;

#ifdef OAL_ILTIMING
    if (g_oalILT.active) g_oalILT.interrupts++;
#endif

    // Get pending interrupt
    irq = INREG32(&g_pIntcL1Regs->SIR_IRQ);

    // First check if it is interrupt from cascade controller
    if (irq != IRQ_L2IRQ) {
        
        // It isn't cascade interrupt, check for GPIO interrupts
        switch (irq) {
        case IRQ_GPIO1:
            irq = IRQ_GPIO_0;
            pGPIORegs=g_pGPIO1Regs;
            break;
        case IRQ_GPIO2:
            irq = IRQ_GPIO_32;
            pGPIORegs=g_pGPIO2Regs;
            break;
        case IRQ_GPIO3:
            irq = IRQ_GPIO_64;
            pGPIORegs=g_pGPIO3Regs;
            break;
        case IRQ_GPIO5:
            irq = IRQ_GPIO_128;
            pGPIORegs=g_pGPIO5Regs;
            break;
        case IRQ_GPIO6:
            irq = IRQ_GPIO_160;
            pGPIORegs=g_pGPIO6Regs;
            break;
        default:
            pGPIORegs = NULL;
            SETREG32(&g_pIntcL1Regs->MIR, 1 << irq);
        }

        // If it is interrupt from GPIOx, find which one, mask and clear it..
        if (pGPIORegs != NULL && (data = INREG32(&pGPIORegs->INTSTAT)) != 0) {
            for (mask = 1; mask != 0; mask <<= 1, irq++) {
                if ((mask & data) != 0) break;
            }
            SETPORT32(&pGPIORegs->INTMASK, mask);
            OUTPORT32(&pGPIORegs->INTSTAT, mask);
        }

    } else {

        // It is interrupt from L2, get number from there
        irq = INREG32(&g_pIntcL2ARegs->SIR_IRQ) + 32;

        // Check for GPIO interrupt
        if (irq == IRQ_GPIO4 && (data = INREG32(&g_pGPIO4Regs->INTSTAT)) != 0) {
            // It is interrupt from GPIO4, find which one, mask and clear it..
            for (irq = IRQ_GPIO_96, mask = 1; mask != 0; mask <<= 1, irq++) {
                if ((mask & data) != 0) break;
            }
            SETPORT32(&g_pGPIO4Regs->INTMASK, mask);
            OUTPORT32(&g_pGPIO4Regs->INTSTAT, mask);
        } else if (irq < 64) {
            // Mask interrupt on L2A
            SETPORT32(&g_pIntcL2ARegs->MIR, 1 << (irq - 32));
        } else {
            // Mask interrupt on L2B
            SETPORT32(&g_pIntcL2BRegs->MIR, 1 << (irq - 64));
        }

        // Acknowledge interrupt on L2
        OUTREG32(&g_pIntcL2ARegs->CNTL, CNTL_NEW_IRQ);
    }

    // Acknowledge interrupt on L1
    OUTREG32(&g_pIntcL1Regs->CNTL, CNTL_NEW_IRQ);

    // Check if this is timer IRQ
    if (irq == g_oalTimerIrq) {
#ifdef OAL_ILTIMING
        if (g_oalILT.active) g_oalILT.interrupts--;
#endif
        // Call timer interrupt handler
        sysIntr = OALTimerIntrHandler();
        // We are done with interrupt
        OALIntrDoneIrqs(1, &irq);
    } else if (irq != OAL_INTR_IRQ_UNDEFINED) {
        // We don't assume IRQ sharing, use static mapping
        sysIntr = OALIntrTranslateIrq(irq);
    }
    
    return sysIntr;
}


//------------------------------------------------------------------------------
//
//  Function:  OALIntrIsIrqPending
//
//  This function checks if the given interrupt is pending.
//
BOOL OALIntrIsIrqPending(UINT32 irq)
{
    BOOL rc = FALSE;

    if (irq < 32) {
        rc = INREG32(&g_pIntcL1Regs->ITR) & (1 << irq);
    } else if (irq < 64) {
        rc = INREG32(&g_pIntcL2ARegs->ITR) & (1 << (irq - 32));
    } else if (irq < 96) {
        rc = INREG32(&g_pIntcL2BRegs->ITR) & (1 << (irq - 64));
    } else if (irq < IRQ_GPIO_32) {
        rc = INREG32(&g_pGPIO1Regs->INTSTAT) & (1 << (irq - IRQ_GPIO_0));
    } else if (irq < IRQ_GPIO_64) {
        rc = INREG32(&g_pGPIO1Regs->INTSTAT) & (1 << (irq - IRQ_GPIO_32));
    } else if (irq < IRQ_GPIO_96) {
        rc = INREG32(&g_pGPIO1Regs->INTSTAT) & (1 << (irq - IRQ_GPIO_64));
    } else if (irq < IRQ_GPIO_128) {
        rc = INREG32(&g_pGPIO1Regs->INTSTAT) & (1 << (irq - IRQ_GPIO_96));
    } else if (irq < IRQ_GPIO_160) {
        rc = INREG32(&g_pGPIO1Regs->INTSTAT) & (1 << (irq - IRQ_GPIO_128));
    } else if (irq < OMAP730_IRQ_MAXIMUM) {
        rc = INREG32(&g_pGPIO1Regs->INTSTAT) & (1 << (irq - IRQ_GPIO_160));
    }

    return (rc != 0);
}

//------------------------------------------------------------------------------