📄 hwinit.s
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ldr r1, =BSP_ULPD_CAM_CLK_CTRL
strh r1, [r0, #OMAP730_ULPD_CAM_CLK_CTRL]
ldr r1, =BSP_ULPD_POWER_CTRL
strh r1, [r0, #OMAP730_ULPD_POWER_CTRL]
ldr r1, =BSP_ULDP_RF_SETUP
strh r1, [r0, #OMAP730_ULPD_RF_SETUP]
ldr r1, =BSP_ULDP_VTCXO_SETUP
strh r1, [r0, #OMAP730_ULPD_VTCXO_SETUP]
ldr r1, =BSP_ULDP_SLICER_SETUP
strh r1, [r0, #OMAP730_ULPD_SLICER_SETUP]
;---------------------------------------------------------------
; Initialize CLKM
;---------------------------------------------------------------
; Code will run from DRAM memory and there can be time before
; new clock will be stabilised and it is safe to access DRAM.
; To avoid any problem we make sure that critical code is
; run from I cache.
;
; First get cache info
mrc p15, 0, r0, c0, c0, 1
; Get I cache line size as (1 << (b[1..0] + 3))
and r3, r0, #3
add r3, r3, #3
mov r2, #1
mov r2, r2, lsl r3
sub r3, r2, #1
; Now get first and last instruction addresses
add r0, pc, #(IC2START - . + 8)
add r1, pc, #(IC2END - . + 8)
; Make sure that address is cache line aligned
add r0, r0, r3
bic r0, r0, r3
; Avoid doing too much
sub r1, r1, #4
; Prefetch instructions
60 mcr p15, 0, r0, c7, c13, 1
add r0, r0, r2
cmp r0, r1
bls %B60
; Initialize base register
ldr r0, =OMAP730_CLKM_REGS_PA
; Remove reset from external peripherals
ldrh r1, [r0, #OMAP730_CLKM_RSTCT2_REGS_OA]
orr r1, r1, #(1 :SHL: 0)
strh r1, [r0, #OMAP730_CLKM_RSTCT2_REGS_OA]
; Read all constants in front (we must avoid D cache miss)
ldr r4, =BSP_CLKM_SYSST
ldr r5, =BSP_CLKM_CKCTL
ldr r6, =BSP_CLKM_DPLL1_CTL
ldr r7, =BSP_CLKM_DELAY
IC2START
; Set the new divisors
nop
nop
nop
nop
nop
nop
nop
nop
strh r5, [r0, #OMAP730_CLKM_CKCTL_REGS_OA]
nop
nop
nop
nop
nop
nop
nop
nop
; Set the new mode
nop
nop
nop
nop
nop
nop
nop
nop
strh r4, [r0, #OMAP730_CLKM_SYSST_REGS_OA]
nop
nop
nop
nop
nop
nop
nop
nop
; Get DPLL1_CTL register address to r1
add r1, r0, #OMAP730_CLKM_DPLL1_CTL_REGS_OA
; Set DPLL divisor/multiplier value
strh r6, [r1]
; Check if requesting that PLL be enabled
tst r6, #(1 :SHL: 4)
beq %F80
; Wait for the PLL lock
70 ldrh r2, [r1]
tst r2, #(1 :SHL: 0)
beq %B70
80
; Delay for new clock stabilitation
mov r1, r7
90 subs r1, r1, #1
bne %B90
IC2END
; Initialize remaining CLKM registers
ldr r1, =BSP_CLKM_IDLECT1
strh r1, [r0, #OMAP730_CLKM_IDLECT1_REGS_OA]
ldr r1, =BSP_CLKM_IDLECT2
strh r1, [r0, #OMAP730_CLKM_IDLECT2_REGS_OA]
ldr r1, =BSP_CLKM_IDLECT3
strh r1, [r0, #OMAP730_CLKM_IDLECT3_REGS_OA]
ldr r1, =BSP_CLKM_EWUPCT
strh r1, [r0, #OMAP730_CLKM_EWUPCT_REGS_OA]
ldr r1, =BSP_CLKM_RSTCT1
strh r1, [r0, #OMAP730_CLKM_RSTCT1_REGS_OA]
ldr r1, =BSP_CLKM_RSTCT2
strh r1, [r0, #OMAP730_CLKM_RSTCT2_REGS_OA]
ldr r1, =BSP_CLKM_CKOUT1
strh r1, [r0, #OMAP730_CLKM_CKOUT1_REGS_OA]
ldr r1, =BSP_CLKM_CKOUT2
strh r1, [r0, #OMAP730_CLKM_CKOUT2_REGS_OA]
;---------------------------------------------------------------
; Configure OMAP730 SoC multiplexing
;---------------------------------------------------------------
ldr r0, =OMAP730_CONFIG_REGS_PA
ldr r1, =BSP_CONFIG_MODE1
str r1, [r0, #OMAP730_CONFIG_MODE1_REGS_OA]
ldr r1, =BSP_CONFIG_MODE2
str r1, [r0, #OMAP730_CONFIG_MODE2_REGS_OA]
ldr r1, =BSP_CONFIG_SPARE1
str r1, [r0, #OMAP730_CONFIG_SPARE1_REGS_OA]
ldr r1, =BSP_CONFIG_SPARE2
str r1, [r0, #OMAP730_CONFIG_SPARE2_REGS_OA]
ldr r1, =BSP_CONFIG_IO_CONFIG0
str r1, [r0, #OMAP730_CONFIG_IO_CONFIG0_REGS_OA]
ldr r1, =BSP_CONFIG_IO_CONFIG1
str r1, [r0, #OMAP730_CONFIG_IO_CONFIG1_REGS_OA]
ldr r1, =BSP_CONFIG_IO_CONFIG2
str r1, [r0, #OMAP730_CONFIG_IO_CONFIG2_REGS_OA]
ldr r1, =BSP_CONFIG_IO_CONFIG3
str r1, [r0, #OMAP730_CONFIG_IO_CONFIG3_REGS_OA]
ldr r1, =BSP_CONFIG_IO_CONFIG4
str r1, [r0, #OMAP730_CONFIG_IO_CONFIG4_REGS_OA]
ldr r1, =BSP_CONFIG_IO_CONFIG5
str r1, [r0, #OMAP730_CONFIG_IO_CONFIG5_REGS_OA]
ldr r1, =BSP_CONFIG_IO_CONFIG6
str r1, [r0, #OMAP730_CONFIG_IO_CONFIG6_REGS_OA]
ldr r1, =BSP_CONFIG_IO_CONFIG7
str r1, [r0, #OMAP730_CONFIG_IO_CONFIG7_REGS_OA]
ldr r1, =BSP_CONFIG_IO_CONFIG8
str r1, [r0, #OMAP730_CONFIG_IO_CONFIG8_REGS_OA]
ldr r1, =BSP_CONFIG_IO_CONFIG9
str r1, [r0, #OMAP730_CONFIG_IO_CONFIG9_REGS_OA]
ldr r1, =BSP_CONFIG_IO_CONFIG10
str r1, [r0, #OMAP730_CONFIG_IO_CONFIG10_REGS_OA]
ldr r1, =BSP_CONFIG_IO_CONFIG11
str r1, [r0, #OMAP730_CONFIG_IO_CONFIG11_REGS_OA]
ldr r1, =BSP_CONFIG_IO_CONFIG12
str r1, [r0, #OMAP730_CONFIG_IO_CONFIG12_REGS_OA]
ldr r1, =BSP_CONFIG_IO_CONFIG13
str r1, [r0, #OMAP730_CONFIG_IO_CONFIG13_REGS_OA]
ldr r1, =BSP_CONFIG_PCC_CONF
str r1, [r0, #OMAP730_CONFIG_PCC_CONF_REGS_OA]
;---------------------------------------------------------------
; Configure OMAP730 SoC GPIO
;---------------------------------------------------------------
ldr r0, =OMAP730_GPIO1_REGS_PA
ldr r1, =BSP_GPIO1_OUT
str r1, [r0, #OMAP730_GPIO_DATAOUT_REGS_OA]
ldr r1, =BSP_GPIO1_DIR
str r1, [r0, #OMAP730_GPIO_DATADIR_REGS_OA]
ldr r1, =BSP_GPIO1_EDGE
str r1, [r0, #OMAP730_GPIO_INTEDGE_REGS_OA]
ldr r0, =OMAP730_GPIO2_REGS_PA
ldr r1, =BSP_GPIO2_OUT
str r1, [r0, #OMAP730_GPIO_DATAOUT_REGS_OA]
ldr r1, =BSP_GPIO2_DIR
str r1, [r0, #OMAP730_GPIO_DATADIR_REGS_OA]
ldr r1, =BSP_GPIO2_EDGE
str r1, [r0, #OMAP730_GPIO_INTEDGE_REGS_OA]
ldr r0, =OMAP730_GPIO3_REGS_PA
ldr r1, =BSP_GPIO3_OUT
str r1, [r0, #OMAP730_GPIO_DATAOUT_REGS_OA]
ldr r1, =BSP_GPIO3_DIR
str r1, [r0, #OMAP730_GPIO_DATADIR_REGS_OA]
ldr r1, =BSP_GPIO3_EDGE
str r1, [r0, #OMAP730_GPIO_INTEDGE_REGS_OA]
ldr r0, =OMAP730_GPIO4_REGS_PA
ldr r1, =BSP_GPIO4_OUT
str r1, [r0, #OMAP730_GPIO_DATAOUT_REGS_OA]
ldr r1, =BSP_GPIO4_DIR
str r1, [r0, #OMAP730_GPIO_DATADIR_REGS_OA]
ldr r1, =BSP_GPIO4_EDGE
str r1, [r0, #OMAP730_GPIO_INTEDGE_REGS_OA]
ldr r0, =OMAP730_GPIO5_REGS_PA
ldr r1, =BSP_GPIO5_OUT
str r1, [r0, #OMAP730_GPIO_DATAOUT_REGS_OA]
ldr r1, =BSP_GPIO5_DIR
str r1, [r0, #OMAP730_GPIO_DATADIR_REGS_OA]
ldr r1, =BSP_GPIO5_EDGE
str r1, [r0, #OMAP730_GPIO_INTEDGE_REGS_OA]
ldr r0, =OMAP730_GPIO6_REGS_PA
ldr r1, =BSP_GPIO6_OUT
str r1, [r0, #OMAP730_GPIO_DATAOUT_REGS_OA]
ldr r1, =BSP_GPIO6_DIR
str r1, [r0, #OMAP730_GPIO_DATADIR_REGS_OA]
ldr r1, =BSP_GPIO6_EDGE
str r1, [r0, #OMAP730_GPIO_INTEDGE_REGS_OA]
;---------------------------------------------------------------
; Disable Watchdog Timer
;---------------------------------------------------------------
ldr r0, =OMAP730_WDOG_REGS_PA
ldr r1, =OMAP730_WDOG_DISABLE_SEQ1
strh r1, [r0, #OMAP730_WDOG_TIMER_MODE]
ldr r1, =OMAP730_WDOG_DISABLE_SEQ2
strh r1, [r0, #OMAP730_WDOG_TIMER_MODE]
;---------------------------------------------------------------
; Set DMA to OMAP3.2 mode
;---------------------------------------------------------------
ldr r0, =OMAP730_DMA_REGS_PA
ldr r1, [r0, #OMAP730_DMA_GSCR_REGS_OA]
orr r1, r1, #(1:SHL:0)
orr r1, r1, #(1:SHL:3)
str r1, [r0, #OMAP730_DMA_GSCR_REGS_OA]
;---------------------------------------------------------------
; Reset USB modules
;---------------------------------------------------------------
ldr r0, =OMAP730_OTG_REGS_PA
ldr r1, =BSP_OTG_SYSCON_1
str r1, [r0, #OMAP730_OTG_SYSCON_1_REGS_OA]
ldr r1, =BSP_OTG_SYSCON_2
str r1, [r0, #OMAP730_OTG_SYSCON_2_REGS_OA]
;-------------------------------------------------------------------------------
END
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