xsc1registerbitspmnc.h

Windows CE 6.0 BSP for VOIPAC Board (PXA270) Version 2b.

//
// Copyright (c) Microsoft Corporation.  All rights reserved.
//
//
// Use of this source code is subject to the terms of the Microsoft end-user
// license agreement (EULA) under which you licensed this SOFTWARE PRODUCT.
// If you did not accept the terms of the EULA, you are not authorized to use
// this source code. For a copy of the EULA, please see the LICENSE.RTF on your
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//
#ifndef __Xsc1RegisterBitsPMNC_H__
#define __Xsc1RegisterBitsPMNC_H__

/* performance monitoring 

REGISTERS (Co-processor 14)
---------------------------
PMNC (CP14 : Reg 0) - Performance Monitor Control 
CCNT (CP14 : Reg 1) - Clock Counter
PMN0 (CP14 : Reg 2) - Performance Counter 0
PMN1 (CP14 : Reg 3) - Performance Counter 1

THE SHORT STORY
---------------
+PMNC specifies what events (from the list below) will be tracked by PMN0 and PMN1, as well as a bunch of other stuff
+When a counter rolls over, IRQ or FIQ is generated as specified by ICMR / ICLR / ICCR
+you can only do this stuff from priv. mode

EVENTS
------
0x0 Instruction cache miss requires fetch from external memory.
0x1 Instruction cache cannot deliver an instruction. This could indicate an ICache miss or an ITLB miss. This event will occur every cycle in which the condition is present.
0x2 Stall due to a data dependency. This event will occur every cycle in which the condition is present.
0x3 Instruction TLB miss.
0x4 Data TLB miss.
0x5 Branch instruction executed, branch may or may not have changed program flow.
0x6 Branch mispredicted. (B and BL instructions only.)
0x7 Instruction executed.
0x8 Stall because the data cache buffers are full. This event will occur every cycle in which the condition is present.
0x9 Stall because the data cache buffers are full. This event will occur once for each contiguous sequence of this type of stall.
0xA Data cache access, not including Cache Operations (defined in Section 7.2.8)
0xB Data cache miss, not including Cache Operations (defined in Section 7.2.8)
0xC Data cache write-back. This event occurs once for each 1/2 line (four words) that are written back from the cache.
0xD Software changed the PC. This event occurs any time the PC is changed by software and there is not a mode change. For example, a mov instruction with PC as the destination will trigger this event. Executing a swi from User mode will not trigger this event, because it will incur a mode change.

0x10 Defined by ASSP
0x11 Defined by ASSP
0x12 Defined by ASSP
0x13 Defined by ASSP
0x14 Defined by ASSP
0x15 Defined by ASSP
0x16 Defined by ASSP
0x17 Defined by ASSP

NOTE: See "Intel XScale Core Developer Manual" Section 8.5 for details

-------------------------------------------------------------------------------------
Mode                         | PMNC.evtCount0               | PMNC.evtCount1
-------------------------------------------------------------------------------------
Instruction Cache Efficiency | 0x7 (instruction count)      | 0x0 (ICache miss)
Data Cache Efficiency        | 0xA (Dcache access)          | 0xB (DCache miss)
Instruction Fetch Latency    | 0x1 (ICache cannot deliver)  | 0x0 (ICache miss)
Data/Bus Request Buffer Full | 0x8 (DBuffer stall duration) | 0x9 (DBuffer stall)
Stall/Writeback Statistics   | 0x2 (data stall)             | 0xC (DCache writeback)
Instruction TLB Efficiency   | 0x7 (instruction count)      | 0x3 (ITLB miss)
Data TLB Efficiency          | 0xA (Dcache access)          | 0x4 (DTLB miss)
-------------------------------------------------------------------------------------

*/

// some bits are reserved, and are write as zero
#if 0
#define PMNC_BIT_RESERVED(n)  (0x1 << n)
#define PMNC_BIT_RESERVED_ALL ( 	PMNC_BIT_RESERVED(7) | \
									PMNC_BIT_RESERVED(11) | \
									PMNC_BIT_RESERVED(28) | \
									PMNC_BIT_RESERVED(29) | \
									PMNC_BIT_RESERVED(30) | \
									PMNC_BIT_RESERVED(31) )
#else									
#define PMNC_BIT_RESERVED_ALL 0xF0000880
#endif

#define PMNC_BIT_RESERVED_MASK (~PMNC_BIT_RESERVED_ALL)


// clear bits that require write-as-zero as per spec
#define PMNC_BIT_RESERVED_CLEAR(dw) (dw &= PMNC_BIT_RESERVED_MASK)

//
// *** PMNC Register ***
//

// Enable (E)
#define PMNC_BIT_E          (0x1)
#define PMNC_BIT_E_SET(dw) (dw |= PMNC_BIT_E)
#define PMNC_BIT_E_DIS(dw) (dw &= ~PMNC_BIT_E)

// Performance Counter Reset(P)
#define PMNC_BIT_P          (0x1 << 1)
#define PMNC_BIT_P_SET(dw) (dw |= PMNC_BIT_P)
#define PMNC_BIT_P_DIS(dw) (dw &= ~PMNC_BIT_P)

// Clock Counter Reset (C)
#define PMNC_BIT_C          (0x1 << 2)
#define PMNC_BIT_C_SET(dw) (dw |= PMNC_BIT_C)
#define PMNC_BIT_C_DIS(dw) (dw &= ~PMNC_BIT_C)

// Clock Counter Divider (D)
#define PMNC_BIT_D          (0x1 << 3)
#define PMNC_BIT_D_SET(dw) (dw |= PMNC_BIT_D)
#define PMNC_BIT_D_DIS(dw) (dw &= ~PMNC_BIT_D)

// perf counter 0 interrupt enable
#define PMNC_BIT_PMN0     (0x1 << 4)       
#define PMNC_BIT_PMN0_SET(dw) (dw |= PMNC_BIT_PMN0)
#define PMNC_BIT_PMN0_DIS(dw) (dw &= ~PMNC_BIT_PMN0)

// perf counter 1 interrupt enable
#define PMNC_BIT_PMN1     (0x1 << 5)
#define PMNC_BIT_PMN1_SET(dw) (dw |= PMNC_BIT_PMN1)
#define PMNC_BIT_PMN1_DIS(dw) (dw &= ~PMNC_BIT_PMN1)

// Clock Counter interrupt enable
#define PMNC_BIT_CCNT     (0x1 << 6)
#define PMNC_BIT_CCNT_SET(dw) (dw |= PMNC_BIT_CCNT)
#define PMNC_BIT_CCNT_DIS(dw) (dw &= ~PMNC_BIT_CCNT)

//
// *** bit 7 reserved ***
//

// perf counter 0 overflow flag
#define PMNC_BIT_PMN0_OVERFLOW (0x1 << 8)
#define PMNC_BIT_PMN0_OVERFLOW_SET(dw) (dw |= PMNC_BIT_PMN0_OVERFLOW)
#define PMNC_BIT_PMN0_OVERFLOW_DIS(dw) (dw &= ~PMNC_BIT_PMN0_OVERFLOW)

// perf counter 1 overflow flag
#define PMNC_BIT_PMN1_OVERFLOW (0x1 << 9)
#define PMNC_BIT_PMN1_OVERFLOW_SET(dw) (dw |= PMNC_BIT_PMN1_OVERFLOW) 
#define PMNC_BIT_PMN1_OVERFLOW_DIS(dw) (dw &= ~PMNC_BIT_PMN1_OVERFLOW)

// clock overflow flag
#define PMNC_BIT_CCNT_OVERFLOW (0x1 << 10)
#define PMNC_BIT_CCNT_OVERFLOW_SET(dw) (dw |= PMNC_BIT_CCNT_OVERFLOW)
#define PMNC_BIT_CCNT_OVERFLOW_DIS(dw) (dw &= ~PMNC_BIT_CCNT_OVERFLOW)

//
// *** bit 11 reserved ***
//

// event types
#define PMNC_EVT_ICACHE_MISS         0x0 // Instruction cache miss requires fetch from external memory.
#define PMNC_EVT_ICACHE_NODELIVER_C  0x1 // Instruction cache cannot deliver an instruction. This could indicate an ICache miss or an ITLB miss. This event will occur every cycle in which the condition is present.
#define PMNC_EVT_STALL_DATA          0x2 // Stall due to a data dependency. This event will occur every cycle in which the condition is present.
#define PMNC_EVT_INST_TLB_MISS       0x3 // Instruction TLB miss.
#define PMNC_EVT_DATA_TLB_MISS       0x4 // Data TLB miss.
#define PMNC_EVT_BRANCH_EXECUTED     0x5 // Branch instruction executed, branch may or may not have changed program flow.
#define PMNC_EVT_BRANCH_MISPREDICTED 0x6 // Branch mispredicted. (B and BL instructions only.)
#define PMNC_EVT_INST_EXECUTED       0x7 // Instruction executed.
#define PMNC_EVT_STALL_DCACHEFULL_C  0x8 // Stall because the data cache buffers are full. This event will occur every cycle in which the condition is present.
#define PMNC_EVT_STALL_DCACHEFULL    0x9 // Stall because the data cache buffers are full. This event will occur once for each contiguous sequence of this type of stall.
#define PMNC_EVT_DCACHE_ACCESS       0xA // Data cache access, not including Cache Operations (defined in Section 7.2.8)
#define PMNC_EVT_DCACHE_MISS         0xB // Data cache miss, not including Cache Operations (defined in Section 7.2.8)
#define PMNC_EVT_DCACHE_WRITEBACK    0xC // Data cache write-back. This event occurs once for each 1/2 line (four words) that are written back from the cache.
#define PMNC_EVT_PC_SWCHANGE         0xD // Software changed the PC. This event occurs any time the PC is changed by software and there is not a mode change. For example, a mov instruction with PC as the destination will trigger this event. Executing a swi from User mode will not trigger this event, because it will incur a mode change.

#define PMNC_EVTCOUNT0_SET(dw, EVT) (dw |= (EVT << 12) )
#define PMNC_EVTCOUNT0_DIS(dw, EVT) (dw &= ~(EVT << 12) )

#define PMNC_EVTCOUNT1_SET(dw, EVT) (dw |= (EVT << 20) )
#define PMNC_EVTCOUNT1_DIS(dw, EVT) (dw &= ~(EVT << 20) )

// handy, these are the bits that comprise the event counters in PMNC
#define PMNC_EVT_ALLBITS 0x0FFFF000

#define PMNC_EVT_ALLBITS_MASK (~PMNC_EVT_ALLBITS)
#define PMNC_EVT_ALLBITS_CLEAR(dw) (dw &= PMNC_EVT_ALLBITS_MASK)


#define CLEAR_PMNC(dwPMNC) \
    dwPMNC &= ~(PMNC_BIT_E | PMNC_BIT_CCNT | PMNC_BIT_PMN0 | PMNC_BIT_PMN1 | PMNC_EVT_ALLBITS); \
    PMNC_BIT_RESERVED_CLEAR(dwPMNC);


/*
----------------------------------------------------------------------------------------------
Mode                                 | PMNC.evtCount0                  | PMNC.evtCount1
----------------------------------------------------------------------------------------------
PMNC_Cfg_InstructionCacheEfficiency  | 0x7 PMNC_EVT_INST_EXECUTED      | 0x0 PMNC_EVT_ICACHE_MISS
PMNC_Cfg_DataCacheEfficiency         | 0xA PMNC_EVT_DCACHE_ACCESS      | 0xB PMNC_EVT_DCACHE_MISS
PMNC_Cfg_InstructionFetchLatency     | 0x1 PMNC_EVT_ICACHE_NODELIVER_C | 0x0 PMNC_EVT_ICACHE_MISS
PMNC_Cfg_DataReques BufferFull       | 0x8 PMNC_EVT_STALL_DCACHEFULL_C | 0x9 PMNC_EVT_STALL_DCACHEFULL
PMNC_Cfg_StallAndWriteBackStatistics | 0x2 PMNC_EVT_STALL_DATA         | 0xC PMNC_EVT_DCACHE_WRITEBACK
PMNC_Cfg_InstructionTLBEfficiency    | 0x7 PMNC_EVT_INST_EXECUTED      | 0x3 PMNC_EVT_INST_TLB_MISS
PMNC_Cfg_DataTLBEfficiency           | 0xA PMNC_EVT_DCACHE_ACCESS      | 0x4 PMNC_EVT_DATA_TLB_MISS
----------------------------------------------------------------------------------------------
*/

#define PMNC_Cfg_InstructionCacheEfficiency(reg)  PMNC_EVTCOUNT0_SET(reg,PMNC_EVT_INST_EXECUTED);      PMNC_EVTCOUNT1_SET(reg,PMNC_EVT_ICACHE_MISS);
#define PMNC_Cfg_DataCacheEfficiency(reg)         PMNC_EVTCOUNT0_SET(reg,PMNC_EVT_DCACHE_ACCESS);      PMNC_EVTCOUNT1_SET(reg,PMNC_EVT_DCACHE_MISS);
#define PMNC_Cfg_InstructionFetchLatency(reg)     PMNC_EVTCOUNT0_SET(reg,PMNC_EVT_ICACHE_NODELIVER_C); PMNC_EVTCOUNT1_SET(reg,PMNC_EVT_ICACHE_MISS);
#define PMNC_Cfg_DataRequesBufferFull(reg)        PMNC_EVTCOUNT0_SET(reg,PMNC_EVT_STALL_DCACHEFULL_C); PMNC_EVTCOUNT1_SET(reg,PMNC_EVT_STALL_DCACHEFULL);
#define PMNC_Cfg_StallAndWriteBackStatistics(reg) PMNC_EVTCOUNT0_SET(reg,PMNC_EVT_STALL_DATA);         PMNC_EVTCOUNT1_SET(reg,PMNC_EVT_DCACHE_WRITEBACK);
#define PMNC_Cfg_InstructionTLBEfficiency(reg)    PMNC_EVTCOUNT0_SET(reg,PMNC_EVT_INST_EXECUTED);      PMNC_EVTCOUNT1_SET(reg,PMNC_EVT_INST_TLB_MISS);
#define PMNC_Cfg_DataTLBEfficiency(reg)           PMNC_EVTCOUNT0_SET(reg,PMNC_EVT_DCACHE_ACCESS);      PMNC_EVTCOUNT1_SET(reg,PMNC_EVT_DATA_TLB_MISS);

//
// *** bits 27-31 reserved
//




#endif