xllp_ac97.h

Windows CE 6.0 BSP for VOIPAC Board (PXA270) Version 2b.

#define XLLP_AC97_U14_ICSR_ADCS   ( 0x1 << 11 )   // use to check or clear the int status for ADC ready

#define XLLP_AC97_U14_ICSR_TSPX   ( 0x1 << 12 )   // use to check or clear the int status for TSPX
#define XLLP_AC97_U14_ICSR_TSMX   ( 0x1 << 13 )   // use to check or clear the int status for TSMX
#define XLLP_AC97_U14_ICSR_D14    ( 0x1 << 14 )   // Reserved
#define XLLP_AC97_U14_ICSR_OVLS   ( 0x1 << 15 )   // use to check or clear the int status for OVFL

// Touch Screen Control Register (TSCR) defintions

#define XLLP_AC97_U14_TSCR_TSMX_POW   ( 0x1 << 0 )    // TSMX pin is powered
#define XLLP_AC97_U14_TSCR_TSPX_POW   ( 0x1 << 1 )    // TSPX pin is powered
#define XLLP_AC97_U14_TSCR_TSMY_POW   ( 0x1 << 2 )    // TSMY pin is powered
#define XLLP_AC97_U14_TSCR_TSPY_POW   ( 0x1 << 3 )    // TSPY pin is powered

#define XLLP_AC97_U14_TSCR_TSMX_GND   ( 0x1 << 4 )    // TSMX pin is grounded
#define XLLP_AC97_U14_TSCR_TSPX_GND   ( 0x1 << 5 )    // TSPX pin is grounded
#define XLLP_AC97_U14_TSCR_TSMY_GND   ( 0x1 << 6 )    // TSMY pin is grounded
#define XLLP_AC97_U14_TSCR_TSPY_GND   ( 0x1 << 7 )    // TSPY pin is grounded

#define XLLP_AC97_U14_TSCR_INTMO      ( 0x0 << 8 )    // Interrupt Mode
#define XLLP_AC97_U14_TSCR_PREMO      ( 0x1 << 8 )    // Pressure Measurement Mode
#define XLLP_AC97_U14_TSCR_POSMO      ( 0x2 << 8 )    // Position Measurement Mode
#define XLLP_AC97_U14_TSCR_HYSD       ( 0x1 << 10 )   // Hysteresis deactivated
#define XLLP_AC97_U14_TSCR_BIAS       ( 0x1 << 11 )   // Bias circuitry activated

#define XLLP_AC97_U14_TSCR_PX         ( 0x1 << 12 )   // Inverted state of TSPX pin
#define XLLP_AC97_U14_TSCR_MX         ( 0x1 << 13 )   // Inverted state of TSMX pin
#define XLLP_AC97_U14_TSCR_D14        ( 0x1 << 14 )   // Reserved
#define XLLP_AC97_U14_TSCR_D15        ( 0x1 << 15 )   // Reserved

// ADC Control Register (ADCCR) definitions

#define XLLP_AC97_U14_ADCCR_ASE       ( 0x1 << 0 ) // ADC is armed by AS bit and started by rising edge on ADCSYNC pin
#define XLLP_AC97_U14_ADCCR_D1        ( 0x1 << 1 ) // Reserved

#define XLLP_AC97_U14_ADCCR_AI_SHIFT  2
#define XLLP_AC97_U14_ADCCR_AI_TSPX   ( 0x0 << XLLP_AC97_U14_ADCCR_AI_SHIFT )   // ADC source is TSPX
#define XLLP_AC97_U14_ADCCR_AI_TSMX   ( 0x1 << XLLP_AC97_U14_ADCCR_AI_SHIFT )   // ADC source is TSMX
#define XLLP_AC97_U14_ADCCR_AI_TSPY   ( 0x2 << XLLP_AC97_U14_ADCCR_AI_SHIFT )   // ADC source is TSPY
#define XLLP_AC97_U14_ADCCR_AI_TSMY   ( 0x3 << XLLP_AC97_U14_ADCCR_AI_SHIFT )   // ADC source is TSMY
#define XLLP_AC97_U14_ADCCR_AI_AD0    ( 0x4 << XLLP_AC97_U14_ADCCR_AI_SHIFT )   // ADC source is AD0
#define XLLP_AC97_U14_ADCCR_AI_AD1    ( 0x5 << XLLP_AC97_U14_ADCCR_AI_SHIFT )   // ADC source is AD1
#define XLLP_AC97_U14_ADCCR_AI_AD2    ( 0x6 << XLLP_AC97_U14_ADCCR_AI_SHIFT )   // ADC source is AD2
#define XLLP_AC97_U14_ADCCR_AI_AD3    ( 0x7 << XLLP_AC97_U14_ADCCR_AI_SHIFT )   // ADC source is AD3

#define XLLP_AC97_U14_ADCCR_D5        ( 0x1 << 5 )    // Reserved
#define XLLP_AC97_U14_ADCCR_D6        ( 0x1 << 6 )    // Reserved
#define XLLP_AC97_U14_ADCCR_AS        ( 0x1 << 7 )    // Start the ADC conversion seq.

#define XLLP_AC97_U14_ADCCR_D8        ( 0x1 << 8 )    // Reserved
#define XLLP_AC97_U14_ADCCR_D9        ( 0x1 << 9 )    // Reserved
#define XLLP_AC97_U14_ADCCR_D10       ( 0x1 << 10 )   // Reserved
#define XLLP_AC97_U14_ADCCR_D11       ( 0x1 << 11 )   // Reserved

#define XLLP_AC97_U14_ADCCR_D12       ( 0x1 << 12 )   // Reserved
#define XLLP_AC97_U14_ADCCR_D13       ( 0x1 << 13 )   // Reserved
#define XLLP_AC97_U14_ADCCR_D14       ( 0x1 << 14 )   // Reserved
#define XLLP_AC97_U14_ADCCR_AE        ( 0x1 << 15 )   // ADC is activated

// ADC Data Register (ADCDR) definitions

#define XLLP_AC97_U14_ADCDR_MASK      0x3FF           // ADC data register data mask
#define XLLP_AC97_U14_ADCDR_ADV       ( 0x1 << 15 )   // Conversion complete

// Feature Control/Status Register 1 (FCSR1) definitions

#define XLLP_AC97_U14_FCSR1_OVFL      ( 0x1 << 0 )    // ADC overflow status
// bit 1 is reserved
#define XLLP_AC97_U14_FCSR1_GIEN      ( 0x1 << 2 )    // Enable interrupt/wakeup signaling
#define XLLP_AC97_U14_FCSR1_HIPS      ( 0x1 << 3 )    // Activate ADC High Pass Filter
#define XLLP_AC97_U14_FCSR1_DC        ( 0x1 << 4 )    // DC filter is enabled
#define XLLP_AC97_U14_FCSR1_DE        ( 0x1 << 5 )    // De-emphasis is enabled
#define XLLP_AC97_U14_FCSR1_XTM       ( 0x1 << 6 )    // Crystal Oscillator Powerdown Mode

#define XLLP_AC97_U14_FCSR1_M_SHIFT   7
#define XLLP_AC97_U14_FCSR1_M_FLAT    ( 0x00 << XLLP_AC97_U14_FCSR1_M_SHIFT )   // Flat mode
#define XLLP_AC97_U14_FCSR1_M_MIN1    ( 0x1 << XLLP_AC97_U14_FCSR1_M_SHIFT )    // Minimum mode
#define XLLP_AC97_U14_FCSR1_M_MIN2    ( 0x2 << XLLP_AC97_U14_FCSR1_M_SHIFT )    // Minimum mode
#define XLLP_AC97_U14_FCSR1_M_MAX     ( 0x3 << XLLP_AC97_U14_FCSR1_M_SHIFT )    // Maximum mode

#define XLLP_AC97_U14_FCSR1_TR_SHIFT  9   // 2 bits wide, Treble Boost

#define XLLP_AC97_U14_FCSR1_BB_SHIFT  11  // 4 bits wide, Bass Boost
// Bit 15 Reserved

// Feature Control/Status Register 2 (FCSR2) definitions

#define XLLP_AC97_U14_FCSR2_EV_SHIFT   0
#define XLLP_AC97_U14_FCSR2_EV_MASK    ( 0x7 << XLLP_AC97_U14_FCSR2_EV_SHIFT ) // Mask for reading or clearing EV */
#define XLLP_AC97_U14_FCSR2_EV_NORMOP  ( 0x0 << XLLP_AC97_U14_FCSR2_EV_SHIFT ) // Set EV for normal operation
#define XLLP_AC97_U14_FCSR2_EV_ACLPBK  ( 0x1 << XLLP_AC97_U14_FCSR2_EV_SHIFT ) // Set EV for ACLink loopback
#define XLLP_AC97_U14_FCSR2_EV_BSLPBK  ( 0x2 << XLLP_AC97_U14_FCSR2_EV_SHIFT ) // Set EV for bitstr loopback
#define XLLP_AC97_U14_FCSR2_EV_DACEVAL ( 0x3 << XLLP_AC97_U14_FCSR2_EV_SHIFT ) // Set EV for DAC bitstr eval
#define XLLP_AC97_U14_FCSR2_EV_ADCEVAL ( 0x4 << XLLP_AC97_U14_FCSR2_EV_SHIFT ) // Set EV for ADC bitstr eval
#define XLLP_AC97_U14_FCSR2_EV_CLKEVAL ( 0x5 << XLLP_AC97_U14_FCSR2_EV_SHIFT ) // Set EV for Clocks eval mode
#define XLLP_AC97_U14_FCSR2_EV_ADC10EV ( 0x6 << XLLP_AC97_U14_FCSR2_EV_SHIFT ) // Set EV for 10 bit ADC eval mode
#define XLLP_AC97_U14_FCSR2_EV_NORMOP1 ( 0x7 << XLLP_AC97_U14_FCSR2_EV_SHIFT ) // Set EV for normal operation
// Bit 3 Reserved

#define XLLP_AC97_U14_FCSR2_SLP_SHIFT     4
#define XLLP_AC97_U14_FCSR2_SLP_MASK      ( 0x3 << XLLP_AC97_U14_FCSR2_SLP_SHIFT )  // Mask for reading or clearing SLP
#define XLLP_AC97_U14_FCSR2_SLP_NSLP      ( 0x0 << XLLP_AC97_U14_FCSR2_SLP_SHIFT )  // No Smart Low Power Mode
#define XLLP_AC97_U14_FCSR2_SLP_SLPC      ( 0x1 << XLLP_AC97_U14_FCSR2_SLP_SHIFT )  // Smart Low Power Codec
#define XLLP_AC97_U14_FCSR2_SLP_SLPPLL    ( 0x2 << XLLP_AC97_U14_FCSR2_SLP_SHIFT )  // Smart Low Power PLL
#define XLLP_AC97_U14_FCSR2_SLP_SLPALL    ( 0x3 << XLLP_AC97_U14_FCSR2_SLP_SHIFT )  // Smart Low Power Codec & PLL
// Bits 6-15 Reserved

// Test Control Register (TCR) definitions
#define XLLP_AC97_U14_TCR_IDDQ    ( 0x1 << 0 )    // IDDQ testing
#define XLLP_AC97_U14_TCR_ROM     ( 0x1 << 1 )    // ROM testing
#define XLLP_AC97_U14_TCR_RAM     ( 0x1 << 2 )    // RAM testing
#define XLLP_AC97_U14_TCR_VOH     ( 0x1 << 3 )    // VOH testing
#define XLLP_AC97_U14_TCR_VOL     ( 0x1 << 4 )    // VOL testing
#define XLLP_AC97_U14_TCR_TRI     ( 0x1 << 5 )    // Tri-Sate testing
// Bits 7-15 Reserved

/* Other Constants */

// For accessing the Codec mixer registers, each increment of one 32-bit word
//  in processor space increments the addressed mixer register by two.
// This does not cause any ambiguities because only even mixer register 
//  addresses are currently supported (AC '97 spec, R 2.2)
#define XLLP_AC97_CODEC_REGS_PER_WORD   	2

/* Default timeout and holdtime settings */

// timeout in reading and writing codec registers through AC link
#define XLLP_AC97_RW_TIMEOUT_DEF		200	//unit is us

// timeout in waiting for codec's ready signal during setup process
#define XLLP_AC97_SETUP_TIMEOUT_DEF		500	//unit is us

// timeout in waiting for locking the link successfully 
#define XLLP_AC97_LOCK_TIMEOUT_DEF   		300	//unit is us

// timeout in shutting down the link
#define XLLP_AC97_LINKOFF_TIMEOUT_DEF   	500	//unit is us

// holdtime for keeping nReset signal active(low) in AC link
#define XLLP_AC97_COLD_HOLDTIME			100	//unit is us

/*
*******************************************************************************
  XLLP AC97 data structure used in function interface  
*******************************************************************************
*/

typedef enum
{
    XLLP_AC97_CODEC_PRIMARY = 0,
    XLLP_AC97_CODEC_SECONDARY = 1
} XLLP_AC97_CODEC_SEL_T ; 

typedef struct
{
    P_XLLP_GPIO_T 	pGpioReg;
    P_XLLP_CLKMGR_T pClockReg;
    P_XLLP_AC97_T 	pAc97Reg;
    P_XLLP_OST_T 	pOstRegs;
    P_XLLP_INTC_T 	pIntcReg;
    XLLP_UINT32_T 	maxSetupTimeOutUs;
    XLLP_BOOL_T 	useSecondaryCodec;
} XLLP_AC97_CONTEXT_T, *P_XLLP_AC97_CONTEXT_T ;


typedef struct
{
    XLLP_BOOL_T  codecReady ;
} XLLP_AC97_STAT_T ;


/*
*******************************************************************************
  XLLP AC97 Error 
*******************************************************************************
*/

typedef enum
{
    XLLP_AC97_NO_ERROR = 0,
    XLLP_AC97_CODEC_ACCESS_TIMEOUT = 1,
    XLLP_AC97_CODEC_NOT_READY = 2,
    XLLP_AC97_LINK_SHUTDOWN_FAIL = 3,
    XLLP_AC97_INTERNAL_ERROR = 4,
    XLLP_AC97_LINK_LOCK_FAIL = 5
} XLLP_AC97_ERROR_T ;


/*
*******************************************************************************
  XLLP AC97 Functions 
*******************************************************************************
*/

XLLP_AC97_ERROR_T  XllpAc97Init(P_XLLP_AC97_CONTEXT_T pAc97ctxt);
XLLP_AC97_ERROR_T  XllpAc97DeInit(P_XLLP_AC97_CONTEXT_T pAc97ctxt);
XLLP_AC97_ERROR_T  XllpAc97ColdReset(P_XLLP_AC97_CONTEXT_T pAc97ctxt);  
XLLP_AC97_ERROR_T  XllpAc97ShutdownAclink(P_XLLP_AC97_T pAc97Reg, P_XLLP_OST_T pOstRegs);

XLLP_AC97_ERROR_T  XllpAc97Read(XLLP_UINT16_T offset, P_XLLP_UINT16_T pData, 
                P_XLLP_AC97_T pAc97Reg, P_XLLP_OST_T pOstRegs, 
                XLLP_UINT32_T maxRWTimeOutUs, XLLP_AC97_CODEC_SEL_T codecSel); 
XLLP_AC97_ERROR_T  XllpAc97Write(XLLP_UINT16_T offset, XLLP_UINT16_T data, 
                P_XLLP_AC97_T pAc97Reg, P_XLLP_OST_T pOstRegs, XLLP_UINT32_T maxRWTimeOutUs, 
                XLLP_AC97_CODEC_SEL_T codecSel); 
void  XllpAc97GetStatus(XLLP_AC97_STAT_T *pStat, P_XLLP_AC97_T pAc97Reg, XLLP_AC97_CODEC_SEL_T codecSel);

#endif //__XLLP_AC97_H__