xllp_ac97.h

Windows CE 6.0 BSP for VOIPAC Board (PXA270) Version 2b.

//#define  XLLP_AC97_CR_E_ASR_PCM_SURR_DAC_RT 0x2E  // eA PCM Surround DAC rate control
//#define  XLLP_AC97_CR_E_ASR_PCM_LFE_DAC_RT  0x30  // eA PCM Surround DAC rate control
#define    XLLP_AC97_CR_E_ASR_PCM_LR_ADC_RT   0x32  // eA PCM L+R ADC rate control (3+4)
#define    XLLP_AC97_CR_E_ASR_MIC_ADC_RT      0x34  // eA PCM Mic ADC rate control (5)

//  0x36 - 0x38: eA Control registers for the four optional PCM channels
//                 (LFE, CNT, LSR, RSR)
//#define  XLLP_AC97_CR_E_6CH_VOL_C_LFE       0x36  // eA
//#define  XLLP_AC97_CR_E_6CH_VOL_LR_SURR     0x38  // eA
//#define  XLLP_AC97_CR_E_RESERVED_0x3A       0x3A

//
// Rev 2.0 Modem registers
//

//#define XLLP_AC97_CR_E_MDEM_ID                0x3C  // eB
//#define XLLP_AC97_CR_E_MDM_CTRL_STAT          0x3E  // eB
//#define XLLP_AC97_CR_E_MDM_LN1_DAC_ADC_RT     0x40  // eB
//#define XLLP_AC97_CR_E_MDM_LN2_DAC_ADC_RT     0x42  // eB
//#define XLLP_AC97_CR_E_MDM_HNDST_DAC_ADC_RT   0x44  // eB
//#define XLLP_AC97_CR_E_MDM_LN1_DAC_ADC_LVL    0x46  // eB 
//#define XLLP_AC97_CR_E_MDM_LN2_DAC_ADC_LVL    0x48  // eB
//#define XLLP_AC97_CR_E_MDM_HNDST_DAC_ADC_LVL  0x4A  // eB
//#define XLLP_AC97_CR_E_MDM_GPIO_PIN_CNFG      0x4C  // eB
//#define XLLP_AC97_CR_E_MDM_GPIO_PIN_POL_TYPE  0x4E  // eB
//#define XLLP_AC97_CR_E_MDM_GPIO_PIN_STICKY    0x50  // eB
//#define XLLP_AC97_CR_E_MDM_GPIO_PIN_WAKEUP    0x52  // eB
//#define XLLP_AC97_CR_E_MDM_GPIO_PIN_STAT      0x54  // eB
//#define XLLP_AC97_CR_E_MDM_MISC_AFE_CTRL_STAT 0x56  // eB
//#define XLLP_AC97_CR_E_RESERVED_0x58          0x58

//
// 5Ah-7Ah: Vendor Reserved
//

// UCB1400, Philips proprietary.
#define    XLLP_AC97_CR_U14_IO_CTRL_STAT  0x5A  // I/O pin level [0..9]. R/W.
#define    XLLP_AC97_CR_U14_IO_DIRN       0x5C  // Sets In(0) or Out(1) for I/O pins
#define    XLLP_AC97_CR_U14_POS_INT_ENAB  0x5E  // Enables intrpt sgnl on rising edge
#define    XLLP_AC97_CR_U14_NEG_INT_ENAB  0x60  // Enables intrpt sgnl on falling edge
#define    XLLP_AC97_CR_U14_INT_CLR_STAT  0x62  // Reports intrpt status, W clears stat
#define    XLLP_AC97_CR_U14_TS_CTRL       0x64  // Touch Screen Control
#define    XLLP_AC97_CR_U14_ADC_CTRL      0x66  // ADC Control
#define    XLLP_AC97_CR_U14_ADC_DATA      0x68  // ADC Data
#define    XLLP_AC97_CR_U14_FTR_CTRL_STAT1  0x6A  // Feature control + status reg 1
#define    XLLP_AC97_CR_U14_FTR_CTRL_STAT2  0x6C  // Feature control + status reg 2
#define    XLLP_AC97_CR_U14_TEST_CTRL       0x6E  // Only in Vendor Specific Test Mode

//
// 7Ch-7Eh: Vendor ID registers.  Optional but standardized for Plug'n'Play
//
#define    XLLP_AC97_CR_VENDOR_ID1         0x7C  
#define    XLLP_AC97_CR_VENDOR_ID2         0x7E  

#define    XLLP_AC97_CR_MAX               XLLP_AC97_CR_VENDOR_ID2

#define    XLLP_AC97_CR_END_OF_LIST       (XLLP_AC97_CR_MAX +  2)


#define    XLLP_AC97_U14_RR_LOUDNESS ( 0x1 << 5 )    // Loudness (bass boost) supported
#define    XLLP_AC97_U14_RR_20BITDAC ( 0x1 << 7 )    // supports 20 bit DAC
#define XLLP_AC97_U14_RR_20BITADC ( 0x1 << 9 )    // supports 20 bit ADC

// Master Volume Register (MVR) definitions

#define XLLP_AC97_U14_MVR_MR_SHIFT    0               // Volume Right, 6 bits wide
// Bits 6,7 Reserved
#define XLLP_AC97_U14_MVR_ML_SHIFT    8               // Volume Left, 6 bits wide
// Bit 14 Reserved
#define XLLP_AC97_U14_MVR_MM          ( 0x1 << 15 )   // Master Mute

// MIC Volume Register (MCVR) definitions

// Bits 0-5 Reserved
#define XLLP_AC97_U14_MCVR_20DB       ( 0x1 << 6 )    // MIC Volume boosted by 20 dB
// Bits 7-15 Reserved

// Record Select Register (RSR) definitions

#define XLLP_AC97_U14_RSR_SR_SHIFT    0
#define XLLP_AC97_U14_RSR_SR_CL       ( 0x0 << XLLP_AC97_U14_RSR_SR_SHIFT ) // copy from left
#define XLLP_AC97_U14_RSR_SR_LINE     ( 0x100 << XLLP_AC97_U14_RSR_SR_SHIFT )

#define XLLP_AC97_U14_RSR_SL_SHIFT    8
#define XLLP_AC97_U14_RSR_SL_MIC      ( 0x0 << XLLP_AC97_U14_RSR_SL_SHIFT )
#define XLLP_AC97_U14_RSR_SL_LINE     ( 0x100 << XLLP_AC97_U14_RSR_SL_SHIFT )

// Record Gain Register (RGR) definitions

#define XLLP_AC97_U14_RGR_GR_SHIFT    0               // Gain Right, 4 bits wide
// Bits 4-7 Reserved
#define XLLP_AC97_U14_RGR_GL_SHIFT    8               // Gain Left, 4 bits wide
// Bits 12-14 Reserved
#define XLLP_AC97_U14_RGR_RM          ( 0x1 << 15 )   // Record Mute

// General Purpose Register (GPR) definitions

// Bits 0-6 Reserved
#define XLLP_AC97_U14_GPR_LPBK        ( 0x1 << 7 )    // ADC/DAC Loopback Mode
// Bits 8-15 Reserved

// Powerdown Control/Status Register (PCSR) definitions

#define XLLP_AC97_U14_PCSR_ADCR   ( 0x1 << 0 )    // ADC ready to transmit data
#define XLLP_AC97_U14_PCSR_DAC    ( 0x1 << 1 )    // DAC ready to accept data
// Bit 2 Reserved
#define XLLP_AC97_U14_PCSR_REF    ( 0x1 << 3 )    // Vref is up to nominal level
// Bits 4-7 Reserved
#define XLLP_AC97_U14_PCSR_PR0    ( 0x1 << 8 )    // ADC & input path powerdown
#define XLLP_AC97_U14_PCSR_PR1    ( 0x1 << 9 )    // DAC & ouput path powerdown
// Bit 10 Reserved
#define XLLP_AC97_U14_PCSR_PR3    ( 0x1 << 11 )   // Vref powerdown
#define XLLP_AC97_U14_PCSR_PR4    ( 0x1 << 12 )   // Digital interface powerdown
#define XLLP_AC97_U14_PCSR_PR5    ( 0x1 << 13 )   // Internal Clock disable
// Bits 14,15 Reserved

// Extended Audio ID Register (EAIDR) definitions

#define XLLP_AC97_U14_EAIDR_VRA   ( 0x1 << 0 )    // Variable Rate PCM Audio supported
// Bits 1-13 Reserved
#define XLLP_AC97_U14_EAIDR_ID    ( 0x11 << 14 )  // 2 bits wide, Always 0.  UCB1400 is a primary codec

// Extended Audio Status and Control Register (EASCR) definitions

#define XLLP_AC97_U14_EASCR_VRA   ( 0x1 << 0 )    // Enable Variable Rate Audio mode
// Bits 1-15 Reserved

// Audio DAC & ADC Sample Rate Control Register (ADR & AAR) definitions

#define XLLP_AC97_U14_DR_8000     0x1F40  //  8000 samples/sec
#define XLLP_AC97_U14_DR_11025    0x2B11  // 11025 samples/sec
#define XLLP_AC97_U14_DR_16000    0x3E80  // 16000 samples/sec
#define XLLP_AC97_U14_DR_22050    0x5622  // 22050 samples/sec
#define XLLP_AC97_U14_DR_32000    0x7D00  // 32000 samples/sec
#define XLLP_AC97_U14_DR_44100    0xAC44  // 44100 samples/sec
#define XLLP_AC97_U14_DR_48000    0xBB80  // 48000 samples/sec

// I/O Data Register (IODR) and I/O Data Direction (IODIRR) definitions
#define XLLP_AC97_U14_IO0 ( 0x1 << 0 )
#define XLLP_AC97_U14_IO1 ( 0x1 << 1 )
#define XLLP_AC97_U14_IO2 ( 0x1 << 2 )
#define XLLP_AC97_U14_IO3 ( 0x1 << 3 )
#define XLLP_AC97_U14_IO4 ( 0x1 << 4 )
#define XLLP_AC97_U14_IO5 ( 0x1 << 5 )
#define XLLP_AC97_U14_IO6 ( 0x1 << 6 )
#define XLLP_AC97_U14_IO7 ( 0x1 << 7 )
#define XLLP_AC97_U14_IO8 ( 0x1 << 8 )
#define XLLP_AC97_U14_IO9 ( 0x1 << 9 )
// Bits 10-15 Reserved

// Positive INT Enable Register (PIER) definitions

#define XLLP_AC97_U14_PIER_ION0   ( 0x1 << 0 )    // enable falling edge interrupt for I/O pin 0
#define XLLP_AC97_U14_PIER_ION1   ( 0x1 << 1 )    // enable falling edge interrupt for I/O pin 1
#define XLLP_AC97_U14_PIER_ION2   ( 0x1 << 2 )    // enable falling edge interrupt for I/O pin 2
#define XLLP_AC97_U14_PIER_ION3   ( 0x1 << 3 )    // enable falling edge interrupt for I/O pin 3

#define XLLP_AC97_U14_PIER_ION4   ( 0x1 << 4 )    // enable falling edge interrupt for I/O pin 4
#define XLLP_AC97_U14_PIER_ION5   ( 0x1 << 5 )    // enable falling edge interrupt for I/O pin 5
#define XLLP_AC97_U14_PIER_ION6   ( 0x1 << 6 )    // enable falling edge interrupt for I/O pin 6
#define XLLP_AC97_U14_PIER_ION7   ( 0x1 << 7 )    // enable falling edge interrupt for I/O pin 7

#define XLLP_AC97_U14_PIER_ION8   ( 0x1 << 8 )    // enable falling edge interrupt for I/O pin 8
#define XLLP_AC97_U14_PIER_ION9   ( 0x1 << 9 )    // enable falling edge interrupt for I/O pin 9
#define XLLP_AC97_U14_PIER_D10    ( 0x1 << 10 )   // Reserved
#define XLLP_AC97_U14_PIER_ADCP   ( 0x1 << 11 )   // enable falling edge interrupt for ADC Ready

#define XLLP_AC97_U14_PIER_TPXP   ( 0x1 << 12 )   // enable falling edge interrupt for TSPX
#define XLLP_AC97_U14_PIER_TMXP   ( 0x1 << 13 )   // enable falling edge interrupt for TSMX
#define XLLP_AC97_U14_PIER_D14    ( 0x1 << 14 )   // Reserved
#define XLLP_AC97_U14_PIER_OVLP   ( 0x1 << 15 )   // enable falling edge interrupt for OVFL

// Negative INT Enable Register (NIER) definitions

#define XLLP_AC97_U14_NIER_ION0   ( 0x1 << 0 )    // enable falling edge interrupt for I/O pin 0
#define XLLP_AC97_U14_NIER_ION1   ( 0x1 << 1 )    // enable falling edge interrupt for I/O pin 1
#define XLLP_AC97_U14_NIER_ION2   ( 0x1 << 2 )    // enable falling edge interrupt for I/O pin 2
#define XLLP_AC97_U14_NIER_ION3   ( 0x1 << 3 )    // enable falling edge interrupt for I/O pin 3

#define XLLP_AC97_U14_NIER_ION4   ( 0x1 << 4 )    // enable falling edge interrupt for I/O pin 4
#define XLLP_AC97_U14_NIER_ION5   ( 0x1 << 5 )    // enable falling edge interrupt for I/O pin 5
#define XLLP_AC97_U14_NIER_ION6   ( 0x1 << 6 )    // enable falling edge interrupt for I/O pin 6
#define XLLP_AC97_U14_NIER_ION7   ( 0x1 << 7 )    // enable falling edge interrupt for I/O pin 7

#define XLLP_AC97_U14_NIER_ION8   ( 0x1 << 8 )    // enable falling edge interrupt for I/O pin 8
#define XLLP_AC97_U14_NIER_ION9   ( 0x1 << 9 )    // enable falling edge interrupt for I/O pin 9
#define XLLP_AC97_U14_NIER_D10    ( 0x1 << 10 )   // Reserved
#define XLLP_AC97_U14_NIER_ADCN   ( 0x1 << 11 )   // enable falling edge interrupt for ADC Ready

#define XLLP_AC97_U14_NIER_TPXN   ( 0x1 << 12 )   // enable falling edge interrupt for TSPX
#define XLLP_AC97_U14_NIER_TMXN   ( 0x1 << 13 )   // enable falling edge interrupt for TSMX
#define XLLP_AC97_U14_NIER_D14    ( 0x1 << 14 )   // Reserved
#define XLLP_AC97_U14_NIER_OVLN   ( 0x1 << 15 )   // enable falling edge interrupt for OVFL

// INT Clear/Status Register (ICSR) definitions

#define XLLP_AC97_U14_ICSR_IOS0   ( 0x1 << 0 )    // use to check or clear the int status for IO Bit 0
#define XLLP_AC97_U14_ICSR_IOS1   ( 0x1 << 1 )    // use to check or clear the int status for IO Bit 1
#define XLLP_AC97_U14_ICSR_IOS2   ( 0x1 << 2 )    // use to check or clear the int status for IO Bit 2
#define XLLP_AC97_U14_ICSR_IOS3   ( 0x1 << 3 )    // use to check or clear the int status for IO Bit 3

#define XLLP_AC97_U14_ICSR_IOS4   ( 0x1 << 4 )    // use to check or clear the int status for IO Bit 4
#define XLLP_AC97_U14_ICSR_IOS5   ( 0x1 << 5 )    // use to check or clear the int status for IO Bit 5
#define XLLP_AC97_U14_ICSR_IOS6   ( 0x1 << 6 )    // use to check or clear the int status for IO Bit 6
#define XLLP_AC97_U14_ICSR_IOS7   ( 0x1 << 7 )    // use to check or clear the int status for IO Bit 7

#define XLLP_AC97_U14_ICSR_IOS8   ( 0x1 << 8 )    // use to check or clear the int status for IO Bit 8
#define XLLP_AC97_U14_ICSR_IOS9   ( 0x1 << 9 )    // use to check or clear the int status for IO Bit 9
#define XLLP_AC97_U14_ICSR_D10    ( 0x1 << 10 )   // Reserved