xlli_bulverde_defs.inc

Windows CE 6.0 BSP for VOIPAC Board (PXA270) Version 2b.

xlli_MCMEM0_offset    EQU     (0x28)
xlli_MCMEM1_offset    EQU     (0x2C)
xlli_MCATT0_offset    EQU     (0x30)
xlli_MCATT1_offset    EQU     (0x34)
xlli_MCIO0_offset     EQU     (0x38)
xlli_MCIO1_offset     EQU     (0x3C)
xlli_MDMRS_offset     EQU     (0x40)
xlli_BOOT_DEF_offset  EQU     (0x44)
xlli_ARB_CNTL_offset  EQU     (0x48)
xlli_BSCNTR0_offset   EQU     (0x4C)
xlli_BSCNTR1_offset   EQU     (0x50)
xlli_LCDBSCNTR_offset EQU     (0x54)
xlli_MDMRSLP_offset   EQU     (0x58)
xlli_BSCNTR2_offset   EQU     (0x5C)
xlli_BSCNTR3_offset   EQU     (0x60)

; Memory Controller bit defs

xlli_MDREFR_K0DB4     EQU     (0x20000000)    ; Sync Static Clock 0 divide by 4 control/status
xlli_MDREFR_K2FREE    EQU     (0x02000000)    ; Set to force SDCLK[2] to be free running
xlli_MDREFR_K1FREE    EQU     (0x01000000)    ; Set to force SDCLK[1] to be free running
xlli_MDREFR_K0FREE    EQU     (0x00800000)    ; Set to force SDCLK[0] to be free running
xlli_MDREFR_SLFRSH    EQU     (0x00400000)    ; Self Refresh Control Status bit
xlli_MDREFR_APD       EQU     (0x00100000)    ; Auto Power Down bit
xlli_MDREFR_K2DB2     EQU     (0x00080000)    ; SDRAM clock pin 2 divide by 2 control/status
xlli_MDREFR_K2RUN     EQU     (0x00040000)    ; SDRAM clock pin 2 run/control status
xlli_MDREFR_K1DB2     EQU     (0x00020000)    ; SDRAM clock pin 1 divide by 2 control/status
xlli_MDREFR_K1RUN     EQU     (0x00010000)    ; SDRAM clock pin 1 run/control status
xlli_MDREFR_E1PIN     EQU     (0x00008000)    ; SDRAM clock Enable pin 1 level control/status
xlli_MDREFR_K0DB2     EQU     (0x00004000)    ; Sync Static Memory Clock divide by 2 control/status
xlli_MDREFR_K0RUN     EQU     (0x00002000)    ; Sync Static Memory Clock Pin 0
xlli_MDREFR_E0PIN     EQU     (0x00000100)    ; SDRAM clock enable pin 0 (Cotulla ONLY!!)

xlli_MDCNFG_DE0       EQU     (0x00000001)    ; SDRAM enable bit for partition 0
xlli_MDCNFG_DE1       EQU     (0x00000002)    ; SDRAM enable bit for partition 1
xlli_MDCNFG_DE2       EQU     (0x00010000)    ; SDRAM enable bit for partition 2
xlli_MDCNFG_DE3       EQU     (0x00020000)    ; SDRAM enable bit for partition 3
xlli_MDCNFG_DWID0     EQU     (0x00000004)    ; SDRAM bus width (clear = 32 bits, set = 16 bits)
xlli_MDCNFG_DWID2     EQU     (0x00040000)    ; SDRAM bus width (clear = 32 bits, set = 16 bits)
xlli_MDCNFG_DCAC0     EQU     (0x00000008)
xlli_MDCNFG_DCAC2     EQU     (0x00080000)

;
; INTERNAL MEMORY CONTROLLER base address and register offsets from the base address 
;

xlli_IMEMORY_CONFIG_BASE      EQU   (0x58000000)

xlli_IMPMCR_offset   EQU     (0x00)       ; Internal Memory Power Manager Control Register
xlli_IMPMSR_offset   EQU     (0x08)       ; Internal Memory Power Management Status Register


;
; UART Definitions
;
xlli_perif_base                 EQU     (0x40000000)    ; Base address of the peripherals
xlli_ffuart_offset              EQU     (0x00100000)    ; Offset to the Full-Feature UART in the peripheral block
xlli_btuart_offset              EQU     (0x00200000)    ; Offset to the BlueTooth UART in the peripheral block
xlli_stuart_offset              EQU     (0x00700000)    ; Offset to the Standard UART in the peripheral block


xlli_uart_thr_offset            EQU     (0x0)       ;DLAB = 0  WO  8bit - Transmit Holding Register
xlli_uart_rbr_offset            EQU     (0x0)       ;DLAB = 0  RO  8bit - Recieve Buffer Register
xlli_uart_dll_offset            EQU     (0x0)       ;DLAB = 1  RW  8bit - Divisor Latch Low Register
xlli_uart_ier_offset            EQU     (0x4)       ;DLAB = 0  RW  8bit - Interrupt Enable Register
xlli_uart_dlh_offset            EQU     (0x4)       ;DLAB = 1  RW  8bit - Divisor Latch High Register
xlli_uart_iir_offset            EQU     (0x8)       ;DLAB = X  RO  8bit - Interrupt Identification Register
xlli_uart_fcr_offset            EQU     (0x8)       ;DLAB = X  WO  8bit - FIFO Control Register
xlli_uart_lcr_offset            EQU     (0xC)       ;DLAB = X  RW  8bit - Line Control Register
xlli_uart_mcr_offset            EQU     (0x10)      ;DLAB = X  RW  8bit - Modem Control Regiser
xlli_uart_lsr_offset            EQU     (0x14)      ;DLAB = X  RO  8bit - Line Status Register
xlli_uart_msr_offset            EQU     (0x18)      ;DLAB = X  RO  8bit - Modem Status Register
xlli_uart_spr_offset            EQU     (0x1C)      ;DLAB = X  RW  8bit - Scratchpad Register
xlli_uart_isr_offset            EQU     (0x20)      ;DLAB = X  RW  8bit - Slow Infrared Select Register
xlli_uart_for_offset            EQU     (0x24)      ;DLAB = X  RO  FIFO Occupancy Register
xlli_uart_abr_offset            EQU     (0x28)      ;DLAB = X  RW  Autobaud Control Register
xlli_uart_acr_offset            EQU     (0x2C)      ;DLAB = X Autobaud Count Register

;
; INTERRUPT CONTROLLER base address and register offsets from the base address
; 
;

xlli_INTERREGS_PHYSICAL_BASE      EQU     (0x40D00000)

xlli_ICIP_offset      EQU     (0x00)   ; Interrupt Controller IRQ Pending Register
xlli_ICMR_offset      EQU     (0x04)   ; Interrupt Controller Mask Register
xlli_ICLR_offset      EQU     (0x08)   ; Interrupt Controller Level Register
xlli_ICFP_offset      EQU     (0x0C)   ; Interrupt Controller FIQ pending Register
xlli_ICPR_offset      EQU     (0x10)   ; Interrupt Controller Pending Register
xlli_ICCR_offset      EQU     (0x14)   ; Interrupt Controller Control Register
xlli_ICHP_offset      EQU     (0x18)   ; Interrupt Controller Highest Priority Reg
xlli_ICMR2_offset     EQU     (0xA0)   ; Interrupt Controller Mask Register 2
xlli_ICLR2_offset     EQU     (0xA4)   ; Interrupt Controller Level Register 2
xlli_ICCR2_offset     EQU     (0xAC)   ; Interrupt Controller Control Register 2

;
; SSP SERIAL PORTS base address and register offsets from the base address
; 

xlli_SSP_PHYSICAL_BASE EQU    (0x40100000)

xlli_SSCR0_1_offset    EQU    (0x00)   ; SSP 1 Control Regsiter 0
xlli_SSCR1_1_offset    EQU    (0x04)   ; SSP 1 Control Register 1
xlli_SSSR_1_offset     EQU    (0x08)   ; SSP 1 Status Register
xlli_SSITR_1_offset    EQU    (0x0C)   ; SSP 1 Interrupt Test Register
xlli_SSDR_1_offset     EQU    (0x10)   ; SSP 1 Data Write Register/Data Read Register

;
; CLOCK REGISTERS base address and register offsets from the base address
; 

xlli_CLKREGS_PHYSICAL_BASE        EQU     (0x41300000)

xlli_CCCR_offset     EQU     (0x00)    ; Core Clock Configuration Register
xlli_CKEN_offset     EQU     (0x04)    ; Clock-Enable Register
xlli_OSCC_offset     EQU     (0x08)    ; Oscillator Configuration Register
xlli_CCSR_offset     EQU     (0x0C)    ; Core Clock Status Register

xlli_CCCR_A_Bit_Mask EQU     (0x1 << 25)  ; "A" bit is bit 25 in CCCR
;
; OS TIMER REGISTERS base address and register offsets from the base address
; 

xlli_OSTREGS_PHYSICAL_BASE        EQU     (0x40A00000)

xlli_OSMR0_offset    EQU     (0x00)    ; OS Timer Match Register 0
xlli_OSMR1_offset    EQU     (0x04)    ; OS Timer Match Register 1
xlli_OSMR2_offset    EQU     (0x08)    ; OS Timer Match Register 2
xlli_OSMR3_offset    EQU     (0x0C)    ; OS Timer Match Register 3

xlli_OSCR0_offset    EQU     (0x10)    ; OS Timer Count Register 0
xlli_OSSR_offset     EQU     (0x14)    ; OS Timer Status Register
xlli_OWER_offset     EQU     (0x18)    ; OS Timer Watchdog Enable Register
xlli_OIER_offset     EQU     (0x1C)    ; OS Timer Interrupt Enable Register

xlli_OSCR4_offset    EQU     (0x40)    ; OS Timer Count Register 4
xlli_OSCR5_offset    EQU     (0x44)    ; OS Timer Count Register 5
xlli_OSCR6_offset    EQU     (0x48)    ; OS Timer Count Register 6
xlli_OSCR7_offset    EQU     (0x4C)    ; OS Timer Count Register 7
xlli_OSCR8_offset    EQU     (0x50)    ; OS Timer Count Register 8
xlli_OSCR9_offset    EQU     (0x54)    ; OS Timer Count Register 9
xlli_OSCR10_offset   EQU     (0x58)    ; OS Timer Count Register 10
xlli_OSCR11_offset   EQU     (0x5C)    ; OS Timer Count Register 11

xlli_OSMR4_offset    EQU     (0x80)    ; OS Timer Match Register 4
xlli_OSMR5_offset    EQU     (0x84)    ; OS Timer Match Register 5
xlli_OSMR6_offset    EQU     (0x88)    ; OS Timer Match Register 6
xlli_OSMR7_offset    EQU     (0x8C)    ; OS Timer Match Register 7
xlli_OSMR8_offset    EQU     (0x90)    ; OS Timer Match Register 8
xlli_OSMR9_offset    EQU     (0x94)    ; OS Timer Match Register 9
xlli_OSMR10_offset   EQU     (0x98)    ; OS Timer Match Register 10
xlli_OSMR11_offset   EQU     (0x9C)    ; OS Timer Match Register 11

xlli_OMCR4_offset    EQU     (0xC0)    ; OS Timer Match Control Register 4
xlli_OMCR5_offset    EQU     (0xC4)    ; OS Timer Match Control Register 5
xlli_OMCR6_offset    EQU     (0xC8)    ; OS Timer Match Control Register 6
xlli_OMCR7_offset    EQU     (0xCC)    ; OS Timer Match Control Register 7
xlli_OMCR8_offset    EQU     (0xD0)    ; OS Timer Match Control Register 8
xlli_OMCR9_offset    EQU     (0xD4)    ; OS Timer Match Control Register 9
xlli_OMCR10_offset   EQU     (0xD8)    ; OS Timer Match Control Register 10
xlli_OMCR11_offset   EQU     (0xDC)    ; OS Timer Match Control Register 11

xlli_OSSR_ALL        EQU     (0xFFF)   ; Match register status "sticky bits"
xlli_OIER_E1         EQU     (0x002)   ; Interrupt enable bit for match register #1

;
; REAL TIME CLOCK (RTC) REGISTERS base address and register offsets from the base address
; 

xlli_RTCREGS_PHYSICAL_BASE   EQU       (0x40900000)

xlli_RCNR_offset     EQU     (0x00)    ; RTC Counter Register
xlli_RTAR_offset     EQU     (0x04)    ; RTC Alarm Register
xlli_RTSR_offset     EQU     (0x08)    ; RTC Status Register
xlli_RTTR_offset     EQU     (0x0C)    ; RTC Timer Trim Register
xlli_RDCR_offset     EQU     (0x10)    ; RTC Day Counter Register
xlli_RYCR_offset     EQU     (0x14)    ; RTC Year Counter Register 
xlli_RDAR1_offset    EQU     (0x18)    ; RTC Day Alarm Register 1
xlli_RYAR1_offset    EQU     (0x1C)    ; RTC Year Alarm Register 2
xlli_RDAR2_offset    EQU     (0x20)    ; RTC Day Alarm Register 2
xlli_RYAR2_offset    EQU     (0x24)    ; RTC Year Alarm Register 2
xlli_SWCR_offset     EQU     (0x28)    ; Stopwatch Counter Register
xlli_SWAR1_offset    EQU     (0x2C)    ; Stopwatch Alarm Register 1
xlli_SWAR2_offset    EQU     (0x30)    ; Stopwatch Alarm Register 2
xlli_PICR_offset     EQU     (0x34)    ; Periodic Interrupt Counter Register
xlli_PIAR_offset     EQU     (0x38)    ; Periodic Interrupt Alarm Register


; Oscillator Controller bit defs

xlli_OSCC_OOK        EQU     (0x01)    ; Oscillator OK bit
xlli_OSCC_OON        EQU     (0x02)    ; Timekeeping (32.768KHz) Osc bit
xlli_OSCC_TOUT_EN    EQU     (0x04)    ; Timekeeping Output enable
xlli_OSCC_PIO_EN     EQU     (0x08)    ; Processor Oscillator Output Enable
xlli_OSCC_CRI        EQU     (0x10)    ; Processor Oscillator Output Enable

;
; Coprocessor 15 data bits
; 

xlli_control_icache  EQU     (0x1000)  ; bit 12 -  i-cache bit
xlli_control_btb     EQU     (0x0800)  ; bit 11 -  btb bit
xlli_control_r       EQU     (0x0200)  ; Bit 9
xlli_control_s       EQU     (0x0100)  ; Bit 8
xlli_control_dcache  EQU     (0x0004)  ; Bit 2  -  d-cache bit
xlli_control_mmu     EQU     (0x0001)  ; Bit 0  -  MMU bit


;
; CP 15 related settings
;

xlli_PID                   EQU     (0x00)
xlli_DACR                  EQU     (0x01)
xlli_CONTROL_DCACHE        EQU     (0x04)
xlli_CONTROL_MINIDATA_01   EQU     (0x10)
xlli_CONTROL_BTB           EQU     (0x800)   ; Brach Target Buffer bit

;
; register bit masks - RCSR
;
xlli_RCSR_HWR         EQU     (0x01)
xlli_RCSR_WDR         EQU     (0x02)
xlli_RCSR_SMR         EQU     (0x04)
xlli_RCSR_GPR         EQU     (0x08)
xlli_RCSR_ALL         EQU     (0xF)


;
;  CPSR Processor constants

xlli_CPSR_Mode_MASK   EQU       (0x0000001F)
xlli_CPSR_Mode_USR    EQU       (0x10)
xlli_CPSR_Mode_FIQ    EQU       (0x11)
xlli_CPSR_Mode_IRQ    EQU       (0x12)
xlli_CPSR_Mode_SVC    EQU       (0x13)
xlli_CPSR_Mode_ABT    EQU       (0x17)
xlli_CPSR_Mode_UND    EQU       (0x1B)
xlli_CPSR_Mode_SYS    EQU       (0x1F)

xlli_CPSR_I_Bit       EQU       (0x80)
xlli_CPSR_F_Bit       EQU       (0x40)


xlli_PWRMODE_SLEEP    EQU       (0x00000003) ; Value for cp14: Reg7 to induce sleep.

      END