xllp_gpio.h

Windows CE 6.0 BSP for VOIPAC Board (PXA270) Version 2b.

#define XLLP_GPIO_AF_BIT_BB_OB_DAT1_MASK	(0x3u  << 0)
#define XLLP_GPIO_AF_BIT_PCMCIA_nPOE		(0x2u  << 0)
#define XLLP_GPIO_AF_BIT_PCMCIA_nPOE_MASK	(0x3u  << 0)

/* Pin  49  alternate functions */
#define XLLP_GPIO_AF_BIT_nPWE				(0x2u  << 2)
#define XLLP_GPIO_AF_BIT_nPWE_MASK			(0x3u  << 2)

/* Pin  50  alternate functions */
#define XLLP_GPIO_AF_BIT_BB_OB_DAT2			(XLLP_BIT_4)
#define XLLP_GPIO_AF_BIT_BB_OB_DAT2_MASK	(0x3u  << 4)
#define XLLP_GPIO_AF_BIT_PCMCIA_nPIOR		(0x2u  << 4)
#define XLLP_GPIO_AF_BIT_PCMCIA_nPIOR_MASK	(0x3u  << 4)

/* Pin  51  alternate functions */
#define XLLP_GPIO_AF_BIT_BB_OB_DAT3			(XLLP_BIT_6)
#define XLLP_GPIO_AF_BIT_BB_OB_DAT3_MASK	(0x3u  << 6)
#define XLLP_GPIO_AF_BIT_PCMCIA_nPIOW		(0x2u  << 6)
#define XLLP_GPIO_AF_BIT_PCMCIA_nPIOW_MASK	(0x3u  << 6)

/* Pin  52  alternate functions */
#define XLLP_GPIO_AF_BIT_BB_OB_CLK			(XLLP_BIT_8)
#define XLLP_GPIO_AF_BIT_BB_OB_CLK_MASK		(0x3u  << 8)

/* Pin  52  alternate functions */
#define XLLP_GPIO_AF_BIT_SSPSCLK3			(0x2u  << 8)
#define XLLP_GPIO_AF_BIT_SSPSCLK3_MASK		(0x3u  << 8)

/* Pin  53  alternate functions */
#define XLLP_GPIO_AF_BIT_BB_OB_STB			(XLLP_BIT_10)
#define XLLP_GPIO_AF_BIT_BB_OB_STB_MASK		(0x3u  << 10)

/* Pin  54  alternate functions */
#define XLLP_GPIO_AF_BIT_BB_OB_WAIT			(0x2u  << 12)
#define XLLP_GPIO_AF_BIT_BB_OB_WAIT_MASK	(0x3u  << 12)
#define XLLP_GPIO_AF_BIT_PCMCIA_nPCE2		(0x2u  << 12)
#define XLLP_GPIO_AF_BIT_PCMCIA_nPCE2_MASK  (0x3u  << 12)

/* Pin  55  alternate functions */
#define XLLP_GPIO_AF_BIT_BB_IB_DAT1			(0x2u  << 14)
#define XLLP_GPIO_AF_BIT_BB_IB_DAT1_MASK	(0x3u  << 14)
#define XLLP_GPIO_AF_BIT_PCMCIA_nPREG		(0x2u  << 14)
#define XLLP_GPIO_AF_BIT_PCMCIA_nPREG_MASK	(0x3u  << 14)

/* Pin  56  alternate functions */
#define XLLP_GPIO_AF_BIT_PCMCIA_nPWAIT		(XLLP_BIT_16)
#define XLLP_GPIO_AF_BIT_PCMCIA_nPWAIT_MASK	(0x3u  << 16)
#define XLLP_GPIO_AF_BIT_BB_IB_DAT2			(0x2u  << 16)
#define XLLP_GPIO_AF_BIT_BB_IB_DAT2_MASK	(0x3u  << 16)

/* Pin  57  alternate functions */
#define XLLP_GPIO_AF_BIT_PCMCIA_nIOIS16			(XLLP_BIT_18)
#define XLLP_GPIO_AF_BIT_PCMCIA_nIOIS16_MASK	(0x3u  << 18)
#define XLLP_GPIO_AF_BIT_BB_IB_DAT3				(0x2u  << 18)
#define XLLP_GPIO_AF_BIT_BB_IB_DAT3_MASK		(0x3u  << 18)

/* Pin  58  alternate functions */
#define XLLP_GPIO_AF_BIT_L_DD0				(0x2u  << 20)
#define XLLP_GPIO_AF_BIT_L_DD0_MASK			(0x3u  << 20)

/* Pin  59  alternate functions */
#define XLLP_GPIO_AF_BIT_L_DD1				(0x2u  << 22)
#define XLLP_GPIO_AF_BIT_L_DD1_MASK			(0x3u  << 22)

/* Pin  60  alternate functions */
#define XLLP_GPIO_AF_BIT_L_DD2				(0x2u  << 24)
#define XLLP_GPIO_AF_BIT_L_DD2_MASK			(0x3u  << 24)

/* Pin  61  alternate functions */
#define XLLP_GPIO_AF_BIT_L_DD3				(0x2u  << 26)
#define XLLP_GPIO_AF_BIT_L_DD3_MASK			(0x3u  << 26)

/* Pin  62  alternate functions */
#define XLLP_GPIO_AF_BIT_L_DD4				(0x2u  << 28)
#define XLLP_GPIO_AF_BIT_L_DD4_MASK			(0x3u  << 28)

/* Pin  63  alternate functions */
#define XLLP_GPIO_AF_BIT_L_DD5				(0x2u  << 30)
#define XLLP_GPIO_AF_BIT_L_DD5_MASK			(0x3u  << 30)

/* Pin  64  alternate functions */
#define XLLP_GPIO_AF_BIT_L_DD6				(0x2u  << 0)
#define XLLP_GPIO_AF_BIT_L_DD6_MASK			(0x3u  << 0)

/* Pin  65  alternate functions */
#define XLLP_GPIO_AF_BIT_L_DD7				(0x2u  << 2)
#define XLLP_GPIO_AF_BIT_L_DD7_MASK			(0x3u  << 2)

/* Pin  66  alternate functions */
#define XLLP_GPIO_AF_BIT_L_DD8				(0x2u  << 4)
#define XLLP_GPIO_AF_BIT_L_DD8_MASK			(0x3u  << 4)

/* Pin  67  alternate functions */
#define XLLP_GPIO_AF_BIT_L_DD9				(0x2u  << 6)
#define XLLP_GPIO_AF_BIT_L_DD9_MASK			(0x3u  << 6)

/* Pin  68  alternate functions */
#define XLLP_GPIO_AF_BIT_L_DD10				(0x2u  << 8)
#define XLLP_GPIO_AF_BIT_L_DD10_MASK		(0x3u  << 8)

/* Pin  69  alternate functions */
#define XLLP_GPIO_AF_BIT_L_DD11				(0x2u  << 10)
#define XLLP_GPIO_AF_BIT_L_DD11_MASK		(0x3u  << 10)

/* Pin  70  alternate functions */
#define XLLP_GPIO_AF_BIT_L_DD12				(0x2u  << 12)
#define XLLP_GPIO_AF_BIT_L_DD12_MASK		(0x3u  << 12)

/* Pin  71  alternate functions */
#define XLLP_GPIO_AF_BIT_L_DD13				(0x2u  << 14)
#define XLLP_GPIO_AF_BIT_L_DD13_MASK		(0x3u  << 14)

/* Pin  72  alternate functions */
#define XLLP_GPIO_AF_BIT_L_DD14				(0x2u  << 16)
#define XLLP_GPIO_AF_BIT_L_DD14_MASK		(0x3u  << 16)

/* Pin  73  alternate functions */
#define XLLP_GPIO_AF_BIT_L_DD15				(0x2u  << 18)
#define XLLP_GPIO_AF_BIT_L_DD15_MASK		(0x3u  << 18)

/* Pin  74  alternate functions */
#define XLLP_GPIO_AF_BIT_L_FCLK_RD			(0x2u  << 20)
#define XLLP_GPIO_AF_BIT_L_FCLK_RD_MASK		(0x3u  << 20)

/* Pin  75  alternate functions */
#define XLLP_GPIO_AF_BIT_L_LCLK_A0			(0x2u  << 22)
#define XLLP_GPIO_AF_BIT_L_LCLK_A0_MASK		(0x3u  << 22)

/* Pin  76  alternate functions */
#define XLLP_GPIO_AF_BIT_L_PCLK_WR			(0x2u  << 24)
#define XLLP_GPIO_AF_BIT_L_PCLK_WR_MASK		(0x3u  << 24)

/* Pin  77  alternate functions */
#define XLLP_GPIO_AF_BIT_L_BIAS				(0x2u  << 26)
#define XLLP_GPIO_AF_BIT_L_BIAS_MASK		(0x3u  << 26)

/* Pin  78  alternate functions */
#define XLLP_GPIO_AF_BIT_nCS2				(0x2u  << 28)
#define XLLP_GPIO_AF_BIT_nCS2_MASK			(0x3u  << 28)

/* Pin  79  alternate functions */
#define XLLP_GPIO_AF_BIT_PCMCIA_PSKTSEL			(XLLP_BIT_30)
#define XLLP_GPIO_AF_BIT_PCMCIA_PSKTSEL_MASK	(0x3u  << 30)

/* Pin  80  alternate functions */
#define XLLP_GPIO_AF_BIT_nCS4				(0x2u  << 0)
#define XLLP_GPIO_AF_BIT_nCS4_MASK			(0x3u  << 0)

/* Pin  81  alternate functions */
#define XLLP_GPIO_AF_BIT_BB_OB_DAT0			(0x2u  << 2)
#define XLLP_GPIO_AF_BIT_BB_OB_DAT0_MASK	(0x3u  << 2)

/* Pin  81  alternate functions */
#define XLLP_GPIO_AF_BIT_SSPTXD3			(XLLP_BIT_2)
#define XLLP_GPIO_AF_BIT_SSPTXD3_MASK		(0x3u  << 2)

/* Pin  82  alternate functions */
#define XLLP_GPIO_AF_BIT_BB_IB_DAT0			(0x2u  << 4)
#define XLLP_GPIO_AF_BIT_BB_IB_DAT0_MASK	(0x3u  << 4)

/* Pin  82  alternate functions */
#define XLLP_GPIO_AF_BIT_SSPRXD3			(XLLP_BIT_4)
#define XLLP_GPIO_AF_BIT_SSPRXD3_MASK		(0x3u  << 4)

/* Pin  83  alternate functions */
#define XLLP_GPIO_AF_BIT_BB_IB_CLK			(0x2u  << 6)
#define XLLP_GPIO_AF_BIT_BB_IB_CLK_MASK		(0x3u  << 6)

/* Pin  83  alternate functions */
#define XLLP_GPIO_AF_BIT_SSPSFRM3			(XLLP_BIT_6)
#define XLLP_GPIO_AF_BIT_SSPSFRM3_MASK		(0x3u  << 6)

/* Pin  84  alternate functions */
#define XLLP_GPIO_AF_BIT_BB_IB_STB			(0x2u  << 8)
#define XLLP_GPIO_AF_BIT_BB_IB_STB_MASK		(0x3u  << 8)

/* Pin  85  alternate functions */
#define XLLP_GPIO_AF_BIT_PCMCIA_nPCE1	    (XLLP_BIT_10)
#define XLLP_GPIO_AF_BIT_PCMCIA_nPCE1_MASK  (0x3u  << 10)
#define XLLP_GPIO_AF_BIT_BB_IB_WAIT			(0x2u  << 10)
#define XLLP_GPIO_AF_BIT_BB_IB_WAIT_MASK	(0x3u  << 10)

/* Pin  86  alternate functions */
#define XLLP_GPIO_AF_BIT_L_DD16				(0x2u  << 12)
#define XLLP_GPIO_AF_BIT_L_DD16_MASK		(0x3u  << 12)

/* Pin  86  alternate functions */
#define XLLP_GPIO_AF_BIT_PCMCIA_nPCE1_1		 (XLLP_BIT_12)
#define XLLP_GPIO_AF_BIT_PCMCIA_nPCE1_1_MASK (0x3u  << 12)

/* Pin  87  alternate functions */
#define XLLP_GPIO_AF_BIT_L_DD17				(0x2u  << 14)
#define XLLP_GPIO_AF_BIT_L_DD17_MASK		(0x3u  << 14)

/* Pin  87  alternate functions */
#define XLLP_GPIO_AF_BIT_PCMCIA_nPCE1_2		 (XLLP_BIT_14)
#define XLLP_GPIO_AF_BIT_PCMCIA_nPCE1_2_MASK (0x3u  << 14)

/* Pin  88  alternate functions */
#define XLLP_GPIO_AF_BIT_USBHPWR0			(XLLP_BIT_16)
#define XLLP_GPIO_AF_BIT_USBHPWR0_MASK		(0x3u  << 16)

/* Pin  88  alternate functions */
#define XLLP_GPIO_AF_BIT_SSPFRM2			(0x3u  << 16)
#define XLLP_GPIO_AF_BIT_SSPFRM2_MASK		(0x3u  << 16)

/* Pin  89  alternate functions */
#define XLLP_GPIO_AF_BIT_USBHPEN0			(0x2u  << 18)
#define XLLP_GPIO_AF_BIT_USBHPEN0_MASK		(0x3u  << 18)

/* Pin  90  alternate functions */
#define XLLP_GPIO_AF_BIT_URST				(0x2u  << 20)
#define XLLP_GPIO_AF_BIT_URST_MASK			(0x3u  << 20)

/* Pin  90  alternate functions */
#define XLLP_GPIO_AF_BIT_CIF_DD4			(0x3u  << 20)
#define XLLP_GPIO_AF_BIT_CIF_DD4_MASK		(0x3u  << 20)

/* Pin  91  alternate functions */
#define XLLP_GPIO_AF_BIT_UCLK				(0x2u  << 22)
#define XLLP_GPIO_AF_BIT_UCLK_MASK			(0x3u  << 22)

/* Pin  91  alternate functions */
#define XLLP_GPIO_AF_BIT_CIF_DD5			(0x3u  << 22)
#define XLLP_GPIO_AF_BIT_CIF_DD5_MASK		(0x3u  << 22)

/* Pin  92  alternate functions */
#define XLLP_GPIO_AF_BIT_MMDAT0				(XLLP_BIT_24)
#define XLLP_GPIO_AF_BIT_MMDAT0_MASK		(0x3u  << 24)
#define XLLP_GPIO_AF_BIT_MSBS				(0x2u  << 24)
#define XLLP_GPIO_AF_BIT_MSBS_MASK			(0x3u  << 24)

/* Pin  93  alternate functions */
#define XLLP_GPIO_AF_BIT_KP_DKIN0			(XLLP_BIT_26)
#define XLLP_GPIO_AF_BIT_KP_DKIN0_MASK		(0x3u  << 26)

/* Pin  94  alternate functions */
#define XLLP_GPIO_AF_BIT_KP_DKIN1			(XLLP_BIT_28)
#define XLLP_GPIO_AF_BIT_KP_DKIN1_MASK		(0x3u  << 28)

/* Pin  95  alternate functions */
#define XLLP_GPIO_AF_BIT_KP_MKIN6			(0x3u  << 30)
#define XLLP_GPIO_AF_BIT_KP_MKIN6_MASK		(0x3u  << 30)

/* Pin  96  alternate functions */
#define XLLP_GPIO_AF_BIT_KP_MKOUT6			(0x3u  << 0)
#define XLLP_GPIO_AF_BIT_KP_MKOUT6_MASK		(0x3u  << 0)

/* Pin  97  alternate functions */
#define XLLP_GPIO_AF_BIT_KP_MKIN3			(0x3u  << 2)
#define XLLP_GPIO_AF_BIT_KP_MKIN3_MASK		(0x3u  << 2)

/* Pin  98  alternate functions */
#define XLLP_GPIO_AF_BIT_KP_MKIN4			(0x3u  << 4)
#define XLLP_GPIO_AF_BIT_KP_MKIN4_MASK		(0x3u  << 4)

/* Pin  99  alternate functions */
#define XLLP_GPIO_AF_BIT_KP_MKIN5			(0x3u  << 6)
#define XLLP_GPIO_AF_BIT_KP_MKIN5_MASK		(0x3u  << 6)

/* Pin  100  alternate functions */
#define XLLP_GPIO_AF_BIT_KP_MKIN0			(XLLP_BIT_8)
#define XLLP_GPIO_AF_BIT_KP_MKIN0_MASK		(0x3u  << 8)

/* Pin  101  alternate functions */
#define XLLP_GPIO_AF_BIT_KP_MKIN1			(XLLP_BIT_10)
#define XLLP_GPIO_AF_BIT_KP_MKIN1_MASK		(0x3u  << 10)

/* Pin  102  alternate functions */
#define XLLP_GPIO_AF_BIT_KP_MKIN2			(XLLP_BIT_12)
#define XLLP_GPIO_AF_BIT_KP_MKIN2_MASK		(0x3u  << 12)

/* Pin  103  alternate functions */
#define XLLP_GPIO_AF_BIT_KP_MKOUT0			(0x2u  << 14)
#define XLLP_GPIO_AF_BIT_KP_MKOUT0_MASK		(0x3u  << 14)

/* Pin  104  alternate functions */
#define XLLP_GPIO_AF_BIT_KP_MKOUT1			(0x2u  << 16)
#define XLLP_GPIO_AF_BIT_KP_MKOUT1_MASK		(0x3u  << 16)

/* Pin  105  alternate functions */
#define XLLP_GPIO_AF_BIT_KP_MKOUT2			(0x2u  << 18)
#define XLLP_GPIO_AF_BIT_KP_MKOUT2_MASK		(0x3u  << 18)

/* Pin  106  alternate functions */
#define XLLP_GPIO_AF_BIT_KP_MKOUT3			(0x2u  << 20)
#define XLLP_GPIO_AF_BIT_KP_MKOUT3_MASK		(0x3u  << 20)

/* Pin  107  alternate functions */
#define XLLP_GPIO_AF_BIT_KP_MKOUT4			(0x2u  << 22)
#define XLLP_GPIO_AF_BIT_KP_MKOUT4_MASK		(0x3u  << 22)

/* Pin  108  alternate functions */
#define XLLP_GPIO_AF_BIT_KP_MKOUT5			(0x2u  << 24)
#define XLLP_GPIO_AF_BIT_KP_MKOUT_MASK		(0x3u  << 24)

/* Pin  109  alternate functions */
#define XLLP_GPIO_AF_BIT_MSSDIO				(0x2u  << 26)
#define XLLP_GPIO_AF_BIT_MSSDIO_MASK		(0x3u  << 26)
#define XLLP_GPIO_AF_BIT_MMDAT1				(XLLP_BIT_26)
#define XLLP_GPIO_AF_BIT_MMDAT1_MASK		(0x3u  << 26)

/* Pin  110  alternate functions */
#define XLLP_GPIO_AF_BIT_MMDAT2				(XLLP_BIT_28)
#define XLLP_GPIO_AF_BIT_MMDAT2_MASK		(0x3u  << 28)

/* Pin  111  alternate functions */
#define XLLP_GPIO_AF_BIT_MMDAT3				(XLLP_BIT_30)
#define XLLP_GPIO_AF_BIT_MMDAT3_MASK		(0x3u  << 30)

/* Pin  112  alternate functions */
#define XLLP_GPIO_AF_BIT_MMCMD				(XLLP_BIT_0)
#define XLLP_GPIO_AF_BIT_MMCMD_MASK			(0x3u  << 0)
#define XLLP_GPIO_AF_BIT_MSINS				(0x2u  << 0)
#define XLLP_GPIO_AF_BIT_MSINS_MASK			(0x3u  << 0)