xlli_lowlev_init.s
来自「Windows CE 6.0 BSP for VOIPAC Board (PXA」· S 代码 · 共 1,365 行 · 第 1/5 页
S
1,365 行
str r6, [r4, #xlli_GAFR3_L_offset] ; Restore alt function values for GPIOs [111:96]
str r7, [r4, #xlli_GAFR3_U_offset] ; Restore alt function values for GPIOs [127:112]
mov r3, r3, LSL #2 ; Move GPIO bits 103:104 to bit locations 11:10
and r8, r3, #0xC00 ; extract settings for bits 11:10
orr r2, r2, r8 ; Add in to value for system config word
mov r3, r3, LSR #10 ; Move GPIO bits 113 to bit location 9
and r8, r3, #0x400 ; extract setting for bit 9
orr r2, r2, r8 ; Add in to value for system config word
;
; Read back from APB to ensure our writes have completed before continuing
;
ldr r8, [r4, #xlli_GAFR3_U_offset]
;
; r2 now contains the SCR2 register data in bits 11:0
; This value gets ORed with the SCR data in bits 31:16 of r1
;
orr r1, r1, r2 ; Generate the data word to be stored
;
; Update SRAM with the above data
;
ldr r4, =xlli_SCR_data ; Get SRAM address where data is to be stored
str r1, [r4] ; Write the contents to SRAM
mov pc, lr ; Return to calling program
ENDFUNC
LTORG
;******************************************************************************
;
;
; ******************
; * *
; * xlli_GPIO_init * Subroutine
; * *
; ******************
;
; This subroutine sets up the GPIO pins in accordance with the values contained in the platform include file.
;
; NOTES: Written for the Bulverde Processor on the Mainstone Development Platform.
;
xlli_GPIO_init FUNCTION
;
;
;
;
; Get GPIO registers base address and configure all GPIO lines.
;
ldr r0, =xlli_GPIOREGS_PHYSICAL_BASE ; Load the GPIO register block base address
ldr r1, =xlli_GPSR0_value ; Get the pin set values for GPSR0
str r1, [r0, #xlli_GPSR0_offset] ; Write the R0 values
ldr r2, =xlli_GPSR1_value ; Get the pin set values for GPSR1
str r2, [r0, #xlli_GPSR1_offset] ; Write the R1 values
ldr r1, =xlli_GPSR2_value ; Get the pin set values for GPSR2
str r1, [r0, #xlli_GPSR2_offset] ; Write the R2 values
ldr r2, =xlli_GPSR3_value ; Get the pin set values for GPSR3
str r2, [r0, #xlli_GPSR3_offset] ; Write the R3 values
ldr r1, =xlli_GPCR0_value ; Get the pin clear values for GPCR0
str r1, [r0, #xlli_GPCR0_offset] ; Write the R0 values
ldr r2, =xlli_GPCR1_value ; Get the pin clear values for GPCR1
str r2, [r0, #xlli_GPCR1_offset] ; Write the R1 values
ldr r1, =xlli_GPCR2_value ; Get the pin clear values for GPCR2
str r1, [r0, #xlli_GPCR2_offset] ; Write the R2 values
ldr r2, =xlli_GPCR3_value ; Get the pin clear values for GPCR3
str r2, [r0, #xlli_GPCR3_offset] ; Write the R3 values
ldr r1, =xlli_GPDR0_value ; Get the pin direction values for GPDR0
str r1, [r0, #xlli_GPDR0_offset] ; Write the R0 values
ldr r2, =xlli_GPDR1_value ; Get the pin direction values for GPDR1
str r2, [r0, #xlli_GPDR1_offset] ; Write the R1 values
ldr r1, =xlli_GPDR2_value ; Get the pin direction values for GPDR2
str r1, [r0, #xlli_GPDR2_offset] ; Write the R2 values
ldr r2, =xlli_GPDR3_value ; Get the pin direction values for GPDR3
str r2, [r0, #xlli_GPDR3_offset] ; Write the R3 values
ldr r1, =xlli_GAFR0_L_value ; Get the pin alt function values for GAFR0_L
str r1, [r0, #xlli_GAFR0_L_offset] ; Write the R0_L values
ldr r2, =xlli_GAFR0_U_value ; Get the pin alt function values for GAFR0_U
str r2, [r0, #xlli_GAFR0_U_offset] ; Write the R0_U values
ldr r1, =xlli_GAFR1_L_value ; Get the pin alt function values for GAFR1_L
str r1, [r0, #xlli_GAFR1_L_offset] ; Write the R1_L values
ldr r2, =xlli_GAFR1_U_value ; Get the pin alt function values for GAFR1_U
str r2, [r0, #xlli_GAFR1_U_offset] ; Write the R1_U values
ldr r1, =xlli_GAFR2_L_value ; Get the pin alt function values for GAFR2_L
str r1, [r0, #xlli_GAFR2_L_offset] ; Write the R2_L values
ldr r2, =xlli_GAFR2_U_value ; Get the pin alt function values for GAFR2_U
str r2, [r0, #xlli_GAFR2_U_offset] ; Write the R2_U values
ldr r1, =xlli_GAFR3_L_value ; Get the pin alt function values for GAFR3_L
str r1, [r0, #xlli_GAFR3_L_offset] ; Write the R3_L values
ldr r2, =xlli_GAFR3_U_value ; Get the pin alt function values for GAFR3_U
str r2, [r0, #xlli_GAFR3_U_offset] ; Write the R3_U values
;
; The RDH and PH bits on Bulverde must be set to enable updated GPIO pins.
; These are sticky bits.
;
ldr r0, =xlli_PMRCREGS_PHYSICAL_BASE
mov r2, #(xlli_PSSR_PH | xlli_PSSR_RDH) ; Set the PH and RDH bits to enable all GPIOs
str r2, [r0, #xlli_PSSR_offset] ; Enable all GPIO lines
;
; Read back from APB to ensure our writes have completed before continuing
;
ldr r2, [r0, #xlli_PSSR_offset]
mov pc, lr ; Return to calling program
ENDFUNC
LTORG
;**************************************************************************************************
;
; **************************************************
; ********** **********
; ********** INITIALIZE MEMORY CONTROLLER **********
; ********** **********
; **************************************************
;
; The sequence below is based on the recommended memory initializing steps detailed
; in the Bulverde EAS, Volume I (Section 13.17, page 13-72)
;
xlli_mem_init FUNCTION
;
; ***** STEP 1: *****
;
; Delay 200 uS
;
ldr r2, =xlli_OSTREGS_PHYSICAL_BASE ; Load OS timer base address
ldr r3, [r2, #xlli_OSCR0_offset] ; Fetch starting value of OSCR0
add r3, r3, #0x300 ; Really 0x2E1 is about 200usec, so 0x300 should be plenty
xlli_3 ldr r1, [r2, #xlli_OSCR0_offset] ; Fetch current OSCR0 value
cmp r1, r3 ; Is the timer past the time out value?
bmi xlli_3 ; No - Loop until it is
;
; STEP 1 - 1st bullet: Write MSC0, MSC1 and MSC2 (the order is not important)
; *******************
;
ldr r4, =xlli_MEMORY_CONFIG_BASE ; Get memory controller base address
ldr r1, =xlli_MSC0_value ; Get MSC0 setting
str r1, [r4, #xlli_MSC0_offset] ; Write the value out
ldr r1, [r4, #xlli_MSC0_offset] ; Read back to latch the data
ldr r2, =xlli_MSC1_value ; Get MSC1 setting
str r2, [r4, #xlli_MSC1_offset] ; Write the value out
ldr r2, [r4, #xlli_MSC1_offset] ; Read back to latch the data
ldr r1, =xlli_MSC2_value ; Get MSC2 setting
str r1, [r4, #xlli_MSC2_offset] ; Write the value out
ldr r1, [r4, #xlli_MSC2_offset] ; Read back to latch the data
;
; STEP 1 - 2nd bullet: Write MECR, MCMEM0, MCMEM1, MCATT0, MCATT1, MCIO0, MCIO1 (order not important)
; *******************
;
ldr r2, =xlli_MECR_value ; write MECR
str r2, [r4, #xlli_MECR_offset]
ldr r1, =xlli_MCMEM0_value ; write MCMEM0
str r1, [r4, #xlli_MCMEM0_offset]
ldr r2, =xlli_MCMEM1_value ; write MCMEM1
str r2, [r4, #xlli_MCMEM1_offset]
ldr r1, =xlli_MCATT0_value ; write MCATT0
str r1, [r4, #xlli_MCATT0_offset]
ldr r2, =xlli_MCATT1_value ; write MCATT1
str r2, [r4, #xlli_MCATT1_offset]
ldr r1, =xlli_MCIO0_value ; write MCIO0
str r1, [r4, #xlli_MCIO0_offset]
ldr r2, =xlli_MCIO1_value ; write MCIO1
str r2, [r4, #xlli_MCIO1_offset]
;
; STEP 1 - 3rd bullet: Write FLYCNFG
; *******************
;
ldr r1, =xlli_FLYCNFG_value ; write FLYCNFG
str r1, [r4, #xlli_FLYCNFG_offset]
;
;
; STEP 1 - 4th bullet: SKIPPED (used only when coming out of sleep)
; *******************
;
; (If required, this would be a write to MDCNFG with enable bits deasserted.)
;
; STEP 1 - 5th bullet: update MDREFR settings
; *******************
;
ldr r2, [r4, #xlli_MDREFR_offset] ; Get reset state of MDREFR
mov r2, r2, lsr #0xC ; Shift data 12 bits (0xC) to the right
mov r2, r2, lsl #0xC ; and shift left 12 bits (Clears DRI field)
; because left shifts fill bits with zeros.
ldr r1, =xlli_MDREFR_value ; Fetch MDREFR value for this platform
mov r1, r1, lsl #0x14 ; use shifts to extract the DRI field using
mov r1, r1, lsr #0x14 ; same method as before but shifting 20 (0x14)
; bits left, then right again.
orr r2, r2, r1 ; insert the DRI field extracted above
str r2, [r4, #xlli_MDREFR_offset] ; write value with valid DRI to MDREFR
orr r2, r2, #xlli_MDREFR_K0RUN ; Enable K0RUN
bic r2, r2, #xlli_MDREFR_K0DB2 ; Configure K0DB2
orr r2, r2, #xlli_MDREFR_K0DB4 ; Set K0DB4 = MemClk/4
bic r2, r2, #(xlli_MDREFR_K1FREE :OR: xlli_MDREFR_K2FREE) ; Clear free run clock bits
orr r2, r2, #xlli_MDREFR_K0FREE ; Set K0FREE (as per Mainstone spec...)
str r2, [r4, #xlli_MDREFR_offset] ; Write back MDREFR
;
; Preserve MDREFR in r2
;
; ***** STEP 2 *****
;
; For systems with Synchronous Flash
;
ldr r1, =xlli_SXCNFG_value
str r1, [r4, #xlli_SXCNFG_offset]
;
; ***** STEP 3 *****
;
; Clear the free run clock bits to enable the use of SDCLK for memory timing
;
bic r2, r2, #(xlli_MDREFR_K2FREE :OR: xlli_MDREFR_K1FREE :OR: xlli_MDREFR_K0FREE)
;
; set K1RUN if bank 0 installed
;
orr r2, r2, #xlli_MDREFR_K1RUN ; Enable SDCLK[1]
orr r2, r2, #xlli_MDREFR_K1DB2 ; Set K1DB2 to halve Memclk
bic r2, r2, #xlli_MDREFR_K2DB2 ; Clear K2DB2
str r2, [r4, #xlli_MDREFR_offset] ; write updated MDREFR
ldr r2, [r4, #xlli_MDREFR_offset] ; read back
bic r2, r2, #xlli_MDREFR_SLFRSH ; Disable self refresh
str r2, [r4, #xlli_MDREFR_offset] ; write updated MDREFR
ldr r2, [r4, #xlli_MDREFR_offset] ; read back
orr r2, r2, #xlli_MDREFR_E1PIN ; Assert E1PIN to enable SDCKE[1]
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