startup.s

Windows CE 6.0 BSP for VOIPAC Board (PXA270) Version 2b.

;
; Copyright (c) Microsoft Corporation.  All rights reserved.
;
;
; Use of this sample source code is subject to the terms of the Microsoft
; license agreement under which you licensed this sample source code. If
; you did not accept the terms of the license agreement, you are not
; authorized to use this sample source code. For the terms of the license,
; please see the license agreement between you and Microsoft or, if applicable,
; see the LICENSE.RTF on your install media or the root of your tools installation.
; THE SAMPLE SOURCE CODE IS PROVIDED "AS IS", WITH NO WARRANTIES.
;
;------------------------------------------------------------------------------
;
;   File:  startup.s
;
;   Kernel startup routine for the Intel Mainstone II board.
;
;------------------------------------------------------------------------------

    INCLUDE kxarm.h
    INCLUDE bulverde.inc
    INCLUDE mainstoneii.inc
    INCLUDE xlli_Bulverde_defs.inc
;    INCLUDE xlli_Mainstone_defs.inc
    
    IMPORT  KernelStart

    TEXTAREA
       
;------------------------------------------------------------------------
    
     
    ; Include memory configuration file with g_oalAddressTable
    ;
    INCLUDE oemaddrtab_cfg.inc

IMAGE_NK_FLASH_OFFSET	EQU		0x80000
IMAGE_NK_FLASH_PA_START	EQU		(MAINSTONEII_BASE_PA_BOOT_FLASH + IMAGE_NK_FLASH_OFFSET)
 
IMAGE_NK_RAM_OFFSET		EQU		0x100000
IMAGE_NK_RAM_PA_START	EQU		(MAINSTONEII_BASE_PA_SDRAM + IMAGE_NK_RAM_OFFSET)

;IMAGE_NK_RAM_SIZE		EQU		0xA00000		; 10MB

;-------------------------------------------------------------------------------
;
; OALStartUp: OEM OAL startup code.
;
; Inputs: None.
; 
; On return: N/A.
;
; Register used: r0
;
;-------------------------------------------------------------------------------
;
    ALIGN
    LEAF_ENTRY OALStartUp

    ; Initialize the hex LEDs on the Mainstone II board.  These use GPIOs which were
    ; configured in the OALXScaleSetFrequencies callback during clock initialization.
    ;
;    bl      Init_HexLEDs
    
    ; Copy the Kernel image from flash to RAM.  The image is configured
    ; to run in RAM, but is stored in flash.  Absolute address references
    ; should be avoided until the image has been relocated and the MMU enabled.
    ;
    ; Check to see if the PC is already in RAM.

	tst		pc, #MAINSTONEII_BASE_PA_SDRAM
	bne		CODEINRAM         ; Done (success).

    ; NOTE: The destination (RAM) address must match the address in the
    ; Kernel's .bib file.  The latter dictates the code fix-up addresses.
    ;
    ldr     r8, =IMAGE_NK_FLASH_PA_START ; Kernel is stored at the base of the boot flash.
                                                   ; Kernel is fixed up to run in SDRAM (this value
                                                   ; must match the NK start address in the .bib file).

    ldr		r4,	[r8, #0x48]
    add		r4,	r4, r8						; ROMHDR offset
    ldr		r1, [r4, #0x08]					; physfirst
    ldr		r2, [r4, #0x0c]					; physlast
    sub		r2, r2, r1						; R2 = total ROM size
    add		r2, r2, #0x100
    
;    ldr     r2, =IMAGE_NK_RAM_SIZE    ; Kernel image length, must be <= the NK
    ldr     r1, =IMAGE_NK_RAM_PA_START   
                                                   
    ; Do 4x32-bit block copies from flash->RAM (corrupts r4-r7).
    ;
10  ldmia   r8!, {r4-r7}        ; Loads from flash (post increment).
    stmia   r1!, {r4-r7}        ; Stores to RAM (post increment).
    subs    r2, r2, #16			; 16-bytes per iteration
    bge     %B10                ; Done?

    ; Now that we've copied ourselves to RAM, jump to the RAM image.  Use the "CodeInRAM" label
    ; to determine the RAM-based code address to which we should jump.
    ;
    add     r2, pc, #CODEINRAM-(.+8)          ; Calculate the relative offset to the 'CodeInRAM' label.
    sub     r2, r2, #IMAGE_NK_FLASH_OFFSET
    ldr     r1, =IMAGE_NK_RAM_PA_START    ; Get the RAM address to which we copied ourself.
    add     r1, r1, r2                        ; Calculate the RAM address of the 'CodeInRAM' label.
    mov     pc, r1                            ;
    nop
    nop
    nop

CODEINRAM

    ; Compute the OEMAddressTable's physical address and 
    ; load it into r0. KernelStart expects r0 to contain
    ; the physical address of this table. The MMU isn't 
    ; turned on until well into KernelStart.  
    ;
    add     r0, pc, #g_oalAddressTable - (. + 8)
    mov     r11, r0
    b       KernelStart
    nop
    nop
    nop
    nop
    nop
    nop
    
STALL
    b       STALL               ; Spin forever.


;-------------------------------------------------------------------------------
;
; Init_HexLEDs: Initializes the Mainstone II board logic to enable the hex LEDs.
;
; Inputs: None.
; 
; On return: N/A.
;
; Register used: r0-r3
;
;-------------------------------------------------------------------------------
;
;    ALIGN
;Init_HexLEDs
;
;    ldr     r3, =BULVERDE_BASE_REG_PA_MEMC
;    ldr     r2, =xlli_MSC1_value
;    str     r2, [r3, #xlli_MSC1_offset]       ; Need to set MSC1 before trying to write to the HEX LEDs
;    ldr     r2, [r3, #xlli_MSC1_offset]       ; Need to read it back to make sure the value latches (see MSC section of manual)
;
;    ldr     r1, =MAINSTONEII_BASE_REG_PA_FPGA
;    mov     r0, #0x0
;    str     r0, [r1, #LEDCTL_OFFSET]          ; Blank hex & discrete leds
;    setHexLED   r1, r0
;
;  IF Interworking :LOR: Thumbing
;    bx       lr
;  ELSE
;    mov      pc, lr                           ; Return to caller.
;  ENDIF
;


;-------------------------------------------------------------------------------
;-------------------------------------------------------------------------------

    LTORG                           ; insert a literal pool here.

;
; TURN_ON_BTB - Enables the Branch Target Buffer
;
; Turn on the BTB via cp15.1[11] - Uses r0
;
;
    LEAF_ENTRY TURN_ON_BTB

    mcr p15, 0, r0, c7, c5, 0   ; flush the icache & BTB
    mrc p15, 0, r0, c1, c0, 0
    orr r0, r0, #0x800
    mcr p15, 0, r0, c1, c0, 0

  IF Interworking :LOR: Thumbing
    bx  lr
  ELSE
    mov  pc, lr          ; return
  ENDIF
   
        
    END 

;------------------------------------------------------------------------------