layout sp with level3.sp

sp files of simple current mirror layout

CIRCUIT example
*
* IC Technology: CMOS 0.12祄 - 6 Metal
*
.op
.dc iref	.1u	220u	.1u
VDD 1 0 DC 1.20
ibias	1	7	DC	200u
iref	1	6	DC	200u
vo	2	0	DC	.3
*
* List of nodes
* "N2" corresponds to n