c8051f020.#1

新华龙c8051f020单片机 串口调试示例程序

/*---------------------------------------------------------------------------
;
;
;
;
; 	FILE NAME  	: C8051F020.H
; 	TARGET MCUs	: C8051F020, 'F021, 'F022, 'F023
; 	DESCRIPTION	: Register/bit definitions for the C8051F02x product family.
;
; 	REVISION 1.1
;
;---------------------------------------------------------------------------*/

/*  BYTE Registers  */
sfr P0       =  0x80;	/* PORT 0                                                  */
sfr SP       =  0x81;	/* STACK POINTER                                           */
sfr DPL      =  0x82;	/* DATA POINTER - LOW BYTE                                 */
sfr DPH      =  0x83;	/* DATA POINTER - HIGH BYTE                                */
sfr P4       =  0x84; 	/* PORT 4																  */
sfr P5       =  0x85; 	/* PORT 5                                                  */
sfr P6       =  0x86; 	/* PORT 6																  */
sfr PCON     =  0x87;	/* POWER CONTROL                                           */
sfr TCON     =  0x88;	/* TIMER CONTROL                                           */
sfr TMOD     =  0x89;	/* TIMER MODE                                              */
sfr TL0      =  0x8A;	/* TIMER 0 - LOW BYTE                                      */
sfr TL1      =  0x8B;	/* TIMER 1 - LOW BYTE                                      */
sfr TH0      =  0x8C;	/* TIMER 0 - HIGH BYTE                                     */
sfr TH1      =  0x8D;	/* TIMER 1 - HIGH BYTE                                     */
sfr CKCON    =  0x8E;	/* CLOCK CONTROL                                           */
sfr PSCTL    =  0x8F;	/* PROGRAM STORE R/W CONTROL                               */
sfr P1       =  0x90;	/* PORT 1                                                  */
sfr TMR3CN   =  0x91;	/* TIMER 3 CONTROL                                         */
sfr TMR3RLL  =  0x92;	/* TIMER 3 RELOAD REGISTER - LOW BYTE                      */
sfr TMR3RLH  =  0x93;	/* TIMER 3 RELOAD REGISTER - HIGH BYTE                     */
sfr TMR3L    =  0x94;	/* TIMER 3 - LOW BYTE                                      */
sfr TMR3H    =  0x95;	/* TIMER 3 - HIGH BYTE                                     */
sfr P7		 =  0x96;   /* PORT 7                                                  */
sfr SCON0    =  0x98;	/* SERIAL PORT 0 CONTROL                                   */
sfr SBUF0    =  0x99;	/* SERIAL PORT 0 BUFFER                                    */
sfr SPI0CFG  =  0x9A;	/* SERIAL PERIPHERAL INTERFACE 0 CONFIGURATION             */
sfr SPI0DAT  =  0x9B;	/* SERIAL PERIPHERAL INTERFACE 0 DATA                      */
sfr ADC1     =  0x9C;   /* ADC 1 DATA                                              */
sfr SPI0CKR  =  0x9D;	/* SERIAL PERIPHERAL INTERFACE 0 CLOCK RATE CONTROL        */
sfr CPT0CN   =  0x9E;	/* COMPARATOR 0 CONTROL                                    */
sfr CPT1CN   =  0x9F;	/* COMPARATOR 1 CONTROL                                    */
sfr P2       =  0xA0;	/* PORT 2                                                  */
sfr EMI0TC   =  0xA1;   /* EMIF TIMING CONTROL                                     */
sfr EMI0CF   =  0xA3;   /* EXTERNAL MEMORY INTERFACE (EMIF) CONFIGURATION          */
sfr P0MDOUT  =  0xA4;	/* PORT 0 OUTPUT MODE CONFIGURATION                        */
sfr P1MDOUT  =  0xA5;	/* PORT 1 OUTPUT MODE CONFIGURATION                        */
sfr P2MDOUT  =  0xA6;	/* PORT 2 OUTPUT MODE CONFIGURATION                        */
sfr P3MDOUT  =  0xA7;	/* PORT 3 OUTPUT MODE CONFIGURATION                        */
sfr IE       =  0xA8;	/* INTERRUPT ENABLE                                        */
sfr SADDR0   =  0xA9;   /* SERIAL PORT 0 SLAVE ADDRESS                             */
sfr ADC1CN   =  0xAA;   /* ADC 1 CONTROL                                           */
sfr ADC1CF   =  0xAB;   /* ADC 1 ANALOG MUX CONFIGURATION                          */
sfr AMX1SL   =  0xAC;   /* ADC 1 ANALOG MUX CHANNEL SELECT                         */
sfr P3IF     =  0xAD;   /* PORT 3 EXTERNAL INTERRUPT FLAGS                         */
sfr SADEN1   =  0xAE;   /* SERIAL PORT 1 SLAVE ADDRESS MASK                        */
sfr EMI0CN   =  0xAF;   /* EXTERNAL MEMORY INTERFACE CONTROL                       */
sfr P3       =  0xB0;	/* PORT 3                                                  */
sfr OSCXCN   =  0xB1;	/* EXTERNAL OSCILLATOR CONTROL                             */
sfr OSCICN   =  0xB2;	/* INTERNAL OSCILLATOR CONTROL                             */
sfr P74OUT   =  0xB5;   /* PORTS 4 - 7 OUTPUT MODE                                 */
sfr FLSCL    =  0xB6;	/* FLASH MEMORY TIMING PRESCALER                           */
sfr FLACL    =  0xB7;	/* FLASH ACESS LIMIT                                       */
sfr IP       =  0xB8;	/* INTERRUPT PRIORITY                                      */
sfr SADEN0   =  0xB9;   /* SERIAL PORT 0 SLAVE ADDRESS MASK                        */
sfr AMX0CF   =  0xBA;	/* ADC 0 MUX CONFIGURATION                                 */
sfr AMX0SL   =  0xBB;	/* ADC 0 MUX CHANNEL SELECTION                             */
sfr ADC0CF   =  0xBC;	/* ADC 0 CONFIGURATION                                     */
sfr P1MDIN   =  0xBD;   /* PORT 1 INPUT MODE                                       */
sfr ADC0L    =  0xBE;	/* ADC 0 DATA - LOW BYTE                                   */
sfr ADC0H    =  0xBF;	/* ADC 0 DATA - HIGH BYTE                                  */
sfr SMB0CN   =  0xC0;	/* SMBUS 0 CONTROL                                         */
sfr SMB0STA  =  0xC1;	/* SMBUS 0 STATUS                                          */
sfr SMB0DAT  =  0xC2;	/* SMBUS 0 DATA                                            */
sfr SMB0ADR  =  0xC3;	/* SMBUS 0 SLAVE ADDRESS                                   */
sfr ADC0GTL  =  0xC4;	/* ADC 0 GREATER-THAN REGISTER - LOW BYTE                  */
sfr ADC0GTH  =  0xC5;	/* ADC 0 GREATER-THAN REGISTER - HIGH BYTE                 */
sfr ADC0LTL  =  0xC6;	/* ADC 0 LESS-THAN REGISTER - LOW BYTE                     */
sfr ADC0LTH  =  0xC7;	/* ADC 0 LESS-THAN REGISTER - HIGH BYTE                    */
sfr T2CON    =  0xC8;	/* TIMER 2 CONTROL                                         */
sfr T4CON    =  0xC9;   /* TIMER 4 CONTROL                                         */
sfr RCAP2L   =  0xCA;	/* TIMER 2 CAPTURE REGISTER - LOW BYTE                     */
sfr RCAP2H   =  0xCB;	/* TIMER 2 CAPTURE REGISTER - HIGH BYTE                    */
sfr TL2      =  0xCC;	/* TIMER 2 - LOW BYTE                                      */
sfr TH2      =  0xCD;	/* TIMER 2 - HIGH BYTE                                     */
sfr SMB0CR   =  0xCF;	/* SMBUS 0 CLOCK RATE                                      */
sfr PSW      =  0xD0;	/* PROGRAM STATUS WORD                                     */
sfr REF0CN   =  0xD1;	/* VOLTAGE REFERENCE 0 CONTROL                             */
sfr DAC0L    =  0xD2;	/* DAC 0 REGISTER - LOW BYTE                               */
sfr DAC0H    =  0xD3;	/* DAC 0 REGISTER - HIGH BYTE                              */
sfr DAC0CN   =  0xD4;	/* DAC 0 CONTROL                                           */
sfr DAC1L    =  0xD5;	/* DAC 1 REGISTER - LOW BYTE                               */
sfr DAC1H    =  0xD6;	/* DAC 1 REGISTER - HIGH BYTE                              */
sfr DAC1CN   =  0xD7;	/* DAC 1 CONTROL                                           */
sfr PCA0CN   =  0xD8;	/* PCA 0 COUNTER CONTROL                                   */
sfr PCA0MD   =  0xD9;	/* PCA 0 COUNTER MODE                                      */
sfr PCA0CPM0 =  0xDA;	/* CONTROL REGISTER FOR PCA 0 MODULE 0                     */
sfr PCA0CPM1 =  0xDB;	/* CONTROL REGISTER FOR PCA 0 MODULE 1                     */
sfr PCA0CPM2 =  0xDC;	/* CONTROL REGISTER FOR PCA 0 MODULE 2                     */
sfr PCA0CPM3 =  0xDD;	/* CONTROL REGISTER FOR PCA 0 MODULE 3                     */
sfr PCA0CPM4 =  0xDE;	/* CONTROL REGISTER FOR PCA 0 MODULE 4                     */
sfr ACC      =  0xE0;	/* ACCUMULATOR                                             */
sfr XBR0     =  0xE1;	/* DIGITAL CROSSBAR CONFIGURATION REGISTER 0               */
sfr XBR1     =  0xE2;	/* DIGITAL CROSSBAR CONFIGURATION REGISTER 1               */
sfr XBR2     =  0xE3;	/* DIGITAL CROSSBAR CONFIGURATION REGISTER 2               */
sfr RCAP4L   =  0xE4;   /* TIMER 4 CAPTURE REGISTER - LOW BYTE                     */
sfr RCAP4H   =  0xE5;   /* TIMER 4 CAPTURE REGISTER - HIGH BYTE                    */
sfr EIE1     =  0xE6;	/* EXTERNAL INTERRUPT ENABLE 1                             */
sfr EIE2     =  0xE7;	/* EXTERNAL INTERRUPT ENABLE 2                             */
sfr ADC0CN   =  0xE8;	/* ADC 0 CONTROL                                           */
sfr PCA0L    =  0xE9;	/* PCA 0 TIMER - LOW BYTE                                  */
sfr PCA0CPL0 =	 0xEA;   /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 0 - LOW BYTE  */
sfr PCA0CPL1 =	 0xEB;   /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 1 - LOW BYTE  */
sfr PCA0CPL2 =	 0xEC;   /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 2 - LOW BYTE  */
sfr PCA0CPL3 =	 0xED;   /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 3 - LOW BYTE  */