📄 count10.rpt
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-- Node name is ':382'
-- Equation name is '_LC2_B21', type is buried
_LC2_B21 = LCELL( _EQ078);
_EQ078 = out70 & !out71 & !out72 & out73;
-- Node name is '~399~1'
-- Equation name is '~399~1', location is LC1_B21, type is buried.
-- synthesized logic cell
_LC1_B21 = LCELL( _EQ079);
_EQ079 = en & !_LC2_B21;
-- Node name is ':399'
-- Equation name is '_LC6_B21', type is buried
_LC6_B21 = LCELL( _EQ080);
_EQ080 = _LC1_B21 & !_LC5_B21 & out73
# _LC1_B21 & !out72 & out73
# _LC1_B21 & _LC5_B21 & out72 & !out73;
-- Node name is ':400'
-- Equation name is '_LC3_B21', type is buried
_LC3_B21 = LCELL( _EQ081);
_EQ081 = _LC1_B21 & !out71 & out72
# _LC1_B21 & !out70 & out72
# _LC1_B21 & out70 & out71 & !out72;
-- Node name is ':401'
-- Equation name is '_LC7_B34', type is buried
_LC7_B34 = LCELL( _EQ082);
_EQ082 = _LC1_B21 & !out70 & out71
# _LC1_B21 & out70 & !out71;
-- Node name is ':439'
-- Equation name is '_LC8_B15', type is buried
!_LC8_B15 = _LC8_B15~NOT;
_LC8_B15~NOT = LCELL( _EQ083);
_EQ083 = !out83
# out82
# out81
# !out80;
-- Node name is '~456~1'
-- Equation name is '~456~1', location is LC3_B1, type is buried.
-- synthesized logic cell
_LC3_B1 = LCELL( _EQ084);
_EQ084 = en & !_LC8_B15;
-- Node name is ':456'
-- Equation name is '_LC7_B15', type is buried
_LC7_B15 = LCELL( _EQ085);
_EQ085 = _LC3_B1 & !_LC6_B15 & out83
# _LC3_B1 & !out82 & out83
# _LC3_B1 & _LC6_B15 & out82 & !out83;
-- Node name is ':457'
-- Equation name is '_LC5_B15', type is buried
_LC5_B15 = LCELL( _EQ086);
_EQ086 = _LC3_B1 & !out81 & out82
# _LC3_B1 & !out80 & out82
# _LC3_B1 & out80 & out81 & !out82;
-- Node name is ':458'
-- Equation name is '_LC1_B15', type is buried
_LC1_B15 = LCELL( _EQ087);
_EQ087 = _LC3_B1 & !out80 & out81
# _LC3_B1 & out80 & !out81;
-- Node name is ':513'
-- Equation name is '_LC2_B22', type is buried
_LC2_B22 = DFFE( out83, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is ':514'
-- Equation name is '_LC1_B9', type is buried
_LC1_B9 = DFFE( out82, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is ':515'
-- Equation name is '_LC3_B17', type is buried
_LC3_B17 = DFFE( out81, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is ':516'
-- Equation name is '_LC1_B1', type is buried
_LC1_B1 = DFFE( out80, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is ':517'
-- Equation name is '_LC2_B29', type is buried
_LC2_B29 = DFFE( out73, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is ':518'
-- Equation name is '_LC1_B28', type is buried
_LC1_B28 = DFFE( out72, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is ':519'
-- Equation name is '_LC4_B34', type is buried
_LC4_B34 = DFFE( out71, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is ':520'
-- Equation name is '_LC1_B34', type is buried
_LC1_B34 = DFFE( out70, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is ':521'
-- Equation name is '_LC3_C33', type is buried
_LC3_C33 = DFFE( out63, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is ':522'
-- Equation name is '_LC2_C27', type is buried
_LC2_C27 = DFFE( out62, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is ':523'
-- Equation name is '_LC7_C31', type is buried
_LC7_C31 = DFFE( out61, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is ':524'
-- Equation name is '_LC6_C31', type is buried
_LC6_C31 = DFFE( out60, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is ':525'
-- Equation name is '_LC7_F19', type is buried
_LC7_F19 = DFFE( out53, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is ':526'
-- Equation name is '_LC1_F20', type is buried
_LC1_F20 = DFFE( out52, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is ':527'
-- Equation name is '_LC2_F24', type is buried
_LC2_F24 = DFFE( out51, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is ':528'
-- Equation name is '_LC5_F24', type is buried
_LC5_F24 = DFFE( out50, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is ':529'
-- Equation name is '_LC1_F4', type is buried
_LC1_F4 = DFFE( out43, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is ':530'
-- Equation name is '_LC2_F1', type is buried
_LC2_F1 = DFFE( out42, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is ':531'
-- Equation name is '_LC4_F3', type is buried
_LC4_F3 = DFFE( out41, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is ':532'
-- Equation name is '_LC6_F3', type is buried
_LC6_F3 = DFFE( out40, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is ':533'
-- Equation name is '_LC6_D21', type is buried
_LC6_D21 = DFFE( out33, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is ':534'
-- Equation name is '_LC7_D35', type is buried
_LC7_D35 = DFFE( out32, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is ':535'
-- Equation name is '_LC1_D24', type is buried
_LC1_D24 = DFFE( _LC3_D26, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is ':536'
-- Equation name is '_LC4_D27', type is buried
_LC4_D27 = DFFE( _LC5_D27, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is ':537'
-- Equation name is '_LC2_B10', type is buried
_LC2_B10 = DFFE( _LC4_B12, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is ':538'
-- Equation name is '_LC2_D18', type is buried
_LC2_D18 = DFFE( _LC3_B12, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is ':539'
-- Equation name is '_LC8_B7', type is buried
_LC8_B7 = DFFE( _LC3_B7, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is ':540'
-- Equation name is '_LC4_B7', type is buried
_LC4_B7 = DFFE( _LC2_B7, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is ':541'
-- Equation name is '_LC2_B3', type is buried
_LC2_B3 = DFFE( _LC8_B3, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is ':542'
-- Equation name is '_LC4_B3', type is buried
_LC4_B3 = DFFE( _LC5_B3, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is ':543'
-- Equation name is '_LC5_B34', type is buried
_LC5_B34 = DFFE( _LC3_B34, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is ':544'
-- Equation name is '_LC6_B7', type is buried
_LC6_B7 = DFFE( _LC1_B7, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is ':556'
-- Equation name is '_LC6_B1', type is buried
_LC6_B1 = DFFE( _EQ088, cout7, VCC, VCC, VCC);
_EQ088 = !clr & en & _LC8_B15
# !en & _LC6_B1
# clr & _LC6_B1;
Project Information e:\frequent\count10.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'ACEX1K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:01
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:01
Fitter 00:00:03
Timing SNF Extractor 00:00:00
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:06
Memory Allocated
-----------------
Peak memory allocated during compilation = 36,220K
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