📄 frequent1.rpt
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Project Information e:\frequent\frequent1.rpt
MAX+plus II Compiler Report File
Version 10.2 07/10/2002
Compiled: 04/24/2007 11:31:43
Copyright (C) 1988-2002 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
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under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
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limited to modification, reverse engineering, de-compiling, or use with
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a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was successful
** DEVICE SUMMARY **
Chip/ Input Output Bidir Memory Memory LCs
POF Device Pins Pins Pins Bits % Utilized LCs % Utilized
frequent1
EP1K30TC144-3 3 33 0 0 0 % 155 8 %
User Pins: 3 33 0
Project Information e:\frequent\frequent1.rpt
** PIN/LOCATION/CHIP ASSIGNMENTS **
Actual
User Assignments
Assignments (if different) Node Name
frequent1@54 clk
frequent1@29 cout
frequent1@30 qout0
frequent1@31 qout1
frequent1@32 qout2
frequent1@33 qout3
frequent1@36 qout4
frequent1@37 qout5
frequent1@38 qout6
frequent1@39 qout7
frequent1@41 qout8
frequent1@42 qout9
frequent1@65 qout10
frequent1@67 qout11
frequent1@68 qout12
frequent1@69 qout13
frequent1@70 qout14
frequent1@72 qout15
frequent1@73 qout16
frequent1@78 qout17
frequent1@79 qout18
frequent1@80 qout19
frequent1@81 qout20
frequent1@82 qout21
frequent1@83 qout22
frequent1@86 qout23
frequent1@87 qout24
frequent1@88 qout25
frequent1@89 qout26
frequent1@90 qout27
frequent1@91 qout28
frequent1@92 qout29
frequent1@95 qout30
frequent1@96 qout31
frequent1@13 rst
frequent1@126 signal
Project Information e:\frequent\frequent1.rpt
** FILE HIERARCHY **
|fre_ctr:ctr1|
|count10:c1|
|count10:c1|lpm_add_sub:557|
|count10:c1|lpm_add_sub:557|addcore:adder|
|count10:c1|lpm_add_sub:557|altshift:result_ext_latency_ffs|
|count10:c1|lpm_add_sub:557|altshift:carry_ext_latency_ffs|
|count10:c1|lpm_add_sub:557|altshift:oflow_ext_latency_ffs|
|count10:c1|lpm_add_sub:558|
|count10:c1|lpm_add_sub:558|addcore:adder|
|count10:c1|lpm_add_sub:558|altshift:result_ext_latency_ffs|
|count10:c1|lpm_add_sub:558|altshift:carry_ext_latency_ffs|
|count10:c1|lpm_add_sub:558|altshift:oflow_ext_latency_ffs|
|count10:c1|lpm_add_sub:559|
|count10:c1|lpm_add_sub:559|addcore:adder|
|count10:c1|lpm_add_sub:559|altshift:result_ext_latency_ffs|
|count10:c1|lpm_add_sub:559|altshift:carry_ext_latency_ffs|
|count10:c1|lpm_add_sub:559|altshift:oflow_ext_latency_ffs|
|count10:c1|lpm_add_sub:560|
|count10:c1|lpm_add_sub:560|addcore:adder|
|count10:c1|lpm_add_sub:560|altshift:result_ext_latency_ffs|
|count10:c1|lpm_add_sub:560|altshift:carry_ext_latency_ffs|
|count10:c1|lpm_add_sub:560|altshift:oflow_ext_latency_ffs|
|count10:c1|lpm_add_sub:561|
|count10:c1|lpm_add_sub:561|addcore:adder|
|count10:c1|lpm_add_sub:561|altshift:result_ext_latency_ffs|
|count10:c1|lpm_add_sub:561|altshift:carry_ext_latency_ffs|
|count10:c1|lpm_add_sub:561|altshift:oflow_ext_latency_ffs|
|count10:c1|lpm_add_sub:562|
|count10:c1|lpm_add_sub:562|addcore:adder|
|count10:c1|lpm_add_sub:562|altshift:result_ext_latency_ffs|
|count10:c1|lpm_add_sub:562|altshift:carry_ext_latency_ffs|
|count10:c1|lpm_add_sub:562|altshift:oflow_ext_latency_ffs|
|count10:c1|lpm_add_sub:563|
|count10:c1|lpm_add_sub:563|addcore:adder|
|count10:c1|lpm_add_sub:563|altshift:result_ext_latency_ffs|
|count10:c1|lpm_add_sub:563|altshift:carry_ext_latency_ffs|
|count10:c1|lpm_add_sub:563|altshift:oflow_ext_latency_ffs|
|count10:c1|lpm_add_sub:564|
|count10:c1|lpm_add_sub:564|addcore:adder|
|count10:c1|lpm_add_sub:564|altshift:result_ext_latency_ffs|
|count10:c1|lpm_add_sub:564|altshift:carry_ext_latency_ffs|
|count10:c1|lpm_add_sub:564|altshift:oflow_ext_latency_ffs|
|latch_32:l1|
Device-Specific Information: e:\frequent\frequent1.rpt
frequent1
***** Logic for device 'frequent1' compiled without errors.
Device: EP1K30TC144-3
ACEX 1K Configuration Scheme: Passive Serial
Device Options:
User-Supplied Start-Up Clock = OFF
Auto-Restart Configuration on Frame Error = OFF
Release Clears Before Tri-States = OFF
Enable Chip_Wide Reset = OFF
Enable Chip-Wide Output Enable = OFF
Enable INIT_DONE Output = OFF
JTAG User Code = 7f
MultiVolt I/O = OFF
R R R R R R R R R R R R R R R R R R R R R R R R R R R
E E E E E E E E E E E E E E E E E E E E E E E E E E E
S S S S S S S S S S S S S S V s S S S S S S S S S S S S S
E E E E E E E E E V E E E E E C i E E E E E E E V E E E E E E
R R R R R R R R R C R R R R R C g R R R R R R R C R R R R R R
V V V V V G V V V V C V V V V G V I n G G G V V V V V V V C V V V V V V
E E E E E N E E E E I E E E E N E N a N N N E E E E E E E I E E E E E E
D D D D D D D D D D O D D D D D D T l D D D D D D D D D D O D D D D D D
--------------------------------------------------------------------------_
/ 144 142 140 138 136 134 132 130 128 126 124 122 120 118 116 114 112 110 |_
/ 143 141 139 137 135 133 131 129 127 125 123 121 119 117 115 113 111 109 |
#TCK | 1 108 | ^DATA0
^CONF_DONE | 2 107 | ^DCLK
^nCEO | 3 106 | ^nCE
#TDO | 4 105 | #TDI
VCCIO | 5 104 | GND
GND | 6 103 | VCCINT
RESERVED | 7 102 | RESERVED
RESERVED | 8 101 | RESERVED
RESERVED | 9 100 | RESERVED
RESERVED | 10 99 | RESERVED
RESERVED | 11 98 | RESERVED
RESERVED | 12 97 | RESERVED
rst | 13 96 | qout31
RESERVED | 14 95 | qout30
GND | 15 94 | VCCIO
VCCINT | 16 93 | GND
RESERVED | 17 92 | qout29
RESERVED | 18 91 | qout28
RESERVED | 19 EP1K30TC144-3 90 | qout27
RESERVED | 20 89 | qout26
RESERVED | 21 88 | qout25
RESERVED | 22 87 | qout24
RESERVED | 23 86 | qout23
VCCIO | 24 85 | VCCINT
GND | 25 84 | GND
RESERVED | 26 83 | qout22
RESERVED | 27 82 | qout21
RESERVED | 28 81 | qout20
cout | 29 80 | qout19
qout0 | 30 79 | qout18
qout1 | 31 78 | qout17
qout2 | 32 77 | ^MSEL0
qout3 | 33 76 | ^MSEL1
#TMS | 34 75 | VCCINT
^nSTATUS | 35 74 | ^nCONFIG
qout4 | 36 73 | qout16
| 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 _|
\ 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 |
\---------------------------------------------------------------------------
q q q G q q R R V R R R R V R G V c G G G G R R V R R R q G q q q q V q
o o o N o o E E C E E E E C E N C l N N N N E E C E E E o N o o o o C o
u u u D u u S S C S S S S C S D C k D D D D S S C S S S u D u u u u C u
t t t t t E E I E E E E I E I E E I E E E t t t t t I t
5 6 7 8 9 R R O R R R R N R N R R O R R R 1 1 1 1 1 O 1
V V V V V V T V T V V V V V 0 1 2 3 4 5
E E E E E E E E E E E E
D D D D D D D D D D D D
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (2.5 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (2.5 volts).
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
$ = Pin has PCI I/O option enabled. Pin is neither '5.0 V'- nor '3.3 V'-tolerant.
Device-Specific Information: e:\frequent\frequent1.rpt
frequent1
** RESOURCE USAGE **
Logic Column Row
Array Interconnect Interconnect Clears/ External
Block Logic Cells Driven Driven Clocks Presets Interconnect
B1 6/ 8( 75%) 3/ 8( 37%) 0/ 8( 0%) 2/2 0/2 4/22( 18%)
B2 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 1/2 0/2 5/22( 22%)
B4 2/ 8( 25%) 1/ 8( 12%) 0/ 8( 0%) 2/2 0/2 2/22( 9%)
B6 4/ 8( 50%) 2/ 8( 25%) 0/ 8( 0%) 2/2 0/2 3/22( 13%)
B8 4/ 8( 50%) 2/ 8( 25%) 0/ 8( 0%) 2/2 0/2 3/22( 13%)
B9 2/ 8( 25%) 1/ 8( 12%) 0/ 8( 0%) 2/2 0/2 2/22( 9%)
B14 7/ 8( 87%) 0/ 8( 0%) 6/ 8( 75%) 2/2 0/2 7/22( 31%)
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