fre_ctr.v

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module	fre_ctr(clk,rst,count_en,count_clr,load);
output	count_en,count_clr,load;
input	clk,rst;
reg		count_en,load;
always @(posedge clk)
  begin
	if(rst) begin count_en=0;load=1; end
	else    begin
			  count_en=~count_en;
			  load=~count_en;          //load信号的产生
            end
  end
assign count_clr=~clk&load;			 //count_clr信号的产生	
endmodule