📄 latch_32.rpt
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-- Node name is 'qo16'
-- Equation name is 'qo16', type is output
qo16 = _LC3_B11;
-- Node name is 'qo17'
-- Equation name is 'qo17', type is output
qo17 = _LC1_C4;
-- Node name is 'qo18'
-- Equation name is 'qo18', type is output
qo18 = _LC5_F29;
-- Node name is 'qo19'
-- Equation name is 'qo19', type is output
qo19 = _LC2_F13;
-- Node name is 'qo20'
-- Equation name is 'qo20', type is output
qo20 = _LC6_C35;
-- Node name is 'qo21'
-- Equation name is 'qo21', type is output
qo21 = _LC5_B8;
-- Node name is 'qo22'
-- Equation name is 'qo22', type is output
qo22 = _LC6_E30;
-- Node name is 'qo23'
-- Equation name is 'qo23', type is output
qo23 = _LC4_C29;
-- Node name is 'qo24'
-- Equation name is 'qo24', type is output
qo24 = _LC8_F16;
-- Node name is 'qo25'
-- Equation name is 'qo25', type is output
qo25 = _LC8_A12;
-- Node name is 'qo26'
-- Equation name is 'qo26', type is output
qo26 = _LC8_D3;
-- Node name is 'qo27'
-- Equation name is 'qo27', type is output
qo27 = _LC1_C17;
-- Node name is 'qo28'
-- Equation name is 'qo28', type is output
qo28 = _LC4_D34;
-- Node name is 'qo29'
-- Equation name is 'qo29', type is output
qo29 = _LC6_D15;
-- Node name is 'qo30'
-- Equation name is 'qo30', type is output
qo30 = _LC6_D28;
-- Node name is 'qo31'
-- Equation name is 'qo31', type is output
qo31 = _LC4_D23;
-- Node name is ':98'
-- Equation name is '_LC4_D23', type is buried
_LC4_D23 = DFFE( din31, GLOBAL( load), VCC, VCC, VCC);
-- Node name is ':99'
-- Equation name is '_LC6_D28', type is buried
_LC6_D28 = DFFE( din30, GLOBAL( load), VCC, VCC, VCC);
-- Node name is ':100'
-- Equation name is '_LC6_D15', type is buried
_LC6_D15 = DFFE( din29, GLOBAL( load), VCC, VCC, VCC);
-- Node name is ':101'
-- Equation name is '_LC4_D34', type is buried
_LC4_D34 = DFFE( din28, GLOBAL( load), VCC, VCC, VCC);
-- Node name is ':102'
-- Equation name is '_LC1_C17', type is buried
_LC1_C17 = DFFE( din27, GLOBAL( load), VCC, VCC, VCC);
-- Node name is ':103'
-- Equation name is '_LC8_D3', type is buried
_LC8_D3 = DFFE( din26, GLOBAL( load), VCC, VCC, VCC);
-- Node name is ':104'
-- Equation name is '_LC8_A12', type is buried
_LC8_A12 = DFFE( din25, GLOBAL( load), VCC, VCC, VCC);
-- Node name is ':105'
-- Equation name is '_LC8_F16', type is buried
_LC8_F16 = DFFE( din24, GLOBAL( load), VCC, VCC, VCC);
-- Node name is ':106'
-- Equation name is '_LC4_C29', type is buried
_LC4_C29 = DFFE( din23, GLOBAL( load), VCC, VCC, VCC);
-- Node name is ':107'
-- Equation name is '_LC6_E30', type is buried
_LC6_E30 = DFFE( din22, GLOBAL( load), VCC, VCC, VCC);
-- Node name is ':108'
-- Equation name is '_LC5_B8', type is buried
_LC5_B8 = DFFE( din21, GLOBAL( load), VCC, VCC, VCC);
-- Node name is ':109'
-- Equation name is '_LC6_C35', type is buried
_LC6_C35 = DFFE( din20, GLOBAL( load), VCC, VCC, VCC);
-- Node name is ':110'
-- Equation name is '_LC2_F13', type is buried
_LC2_F13 = DFFE( din19, GLOBAL( load), VCC, VCC, VCC);
-- Node name is ':111'
-- Equation name is '_LC5_F29', type is buried
_LC5_F29 = DFFE( din18, GLOBAL( load), VCC, VCC, VCC);
-- Node name is ':112'
-- Equation name is '_LC1_C4', type is buried
_LC1_C4 = DFFE( din17, GLOBAL( load), VCC, VCC, VCC);
-- Node name is ':113'
-- Equation name is '_LC3_B11', type is buried
_LC3_B11 = DFFE( din16, GLOBAL( load), VCC, VCC, VCC);
-- Node name is ':114'
-- Equation name is '_LC4_E1', type is buried
_LC4_E1 = DFFE( din15, GLOBAL( load), VCC, VCC, VCC);
-- Node name is ':115'
-- Equation name is '_LC1_F36', type is buried
_LC1_F36 = DFFE( din14, GLOBAL( load), VCC, VCC, VCC);
-- Node name is ':116'
-- Equation name is '_LC4_F10', type is buried
_LC4_F10 = DFFE( din13, GLOBAL( load), VCC, VCC, VCC);
-- Node name is ':117'
-- Equation name is '_LC6_A32', type is buried
_LC6_A32 = DFFE( din12, GLOBAL( load), VCC, VCC, VCC);
-- Node name is ':118'
-- Equation name is '_LC4_C13', type is buried
_LC4_C13 = DFFE( din11, GLOBAL( load), VCC, VCC, VCC);
-- Node name is ':119'
-- Equation name is '_LC1_D4', type is buried
_LC1_D4 = DFFE( din10, GLOBAL( load), VCC, VCC, VCC);
-- Node name is ':120'
-- Equation name is '_LC1_E20', type is buried
_LC1_E20 = DFFE( din9, GLOBAL( load), VCC, VCC, VCC);
-- Node name is ':121'
-- Equation name is '_LC1_D19', type is buried
_LC1_D19 = DFFE( din8, GLOBAL( load), VCC, VCC, VCC);
-- Node name is ':122'
-- Equation name is '_LC6_B19', type is buried
_LC6_B19 = DFFE( din7, GLOBAL( load), VCC, VCC, VCC);
-- Node name is ':123'
-- Equation name is '_LC1_E11', type is buried
_LC1_E11 = DFFE( din6, GLOBAL( load), VCC, VCC, VCC);
-- Node name is ':124'
-- Equation name is '_LC6_A11', type is buried
_LC6_A11 = DFFE( din5, GLOBAL( load), VCC, VCC, VCC);
-- Node name is ':125'
-- Equation name is '_LC1_F11', type is buried
_LC1_F11 = DFFE( din4, GLOBAL( load), VCC, VCC, VCC);
-- Node name is ':126'
-- Equation name is '_LC2_B34', type is buried
_LC2_B34 = DFFE( din3, GLOBAL( load), VCC, VCC, VCC);
-- Node name is ':127'
-- Equation name is '_LC7_C19', type is buried
_LC7_C19 = DFFE( din2, GLOBAL( load), VCC, VCC, VCC);
-- Node name is ':128'
-- Equation name is '_LC8_C4', type is buried
_LC8_C4 = DFFE( din1, GLOBAL( load), VCC, VCC, VCC);
-- Node name is ':129'
-- Equation name is '_LC2_C26', type is buried
_LC2_C26 = DFFE( din0, GLOBAL( load), VCC, VCC, VCC);
Project Information e:\frequent\latch_32.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'ACEX1K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:01
Fitter 00:00:03
Timing SNF Extractor 00:00:00
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:05
Memory Allocated
-----------------
Peak memory allocated during compilation = 32,591K
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