📄 latch_32.rpt
字号:
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: e:\frequent\latch_32.rpt
latch_32
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
12 - - C -- OUTPUT 0 1 0 0 qo0
95 - - C -- OUTPUT 0 1 0 0 qo1
18 - - C -- OUTPUT 0 1 0 0 qo2
9 - - B -- OUTPUT 0 1 0 0 qo3
82 - - F -- OUTPUT 0 1 0 0 qo4
101 - - A -- OUTPUT 0 1 0 0 qo5
87 - - E -- OUTPUT 0 1 0 0 qo6
10 - - B -- OUTPUT 0 1 0 0 qo7
19 - - D -- OUTPUT 0 1 0 0 qo8
26 - - E -- OUTPUT 0 1 0 0 qo9
92 - - D -- OUTPUT 0 1 0 0 qo10
96 - - C -- OUTPUT 0 1 0 0 qo11
8 - - A -- OUTPUT 0 1 0 0 qo12
80 - - F -- OUTPUT 0 1 0 0 qo13
30 - - F -- OUTPUT 0 1 0 0 qo14
86 - - E -- OUTPUT 0 1 0 0 qo15
99 - - B -- OUTPUT 0 1 0 0 qo16
72 - - - 03 OUTPUT 0 1 0 0 qo17
32 - - F -- OUTPUT 0 1 0 0 qo18
81 - - F -- OUTPUT 0 1 0 0 qo19
17 - - C -- OUTPUT 0 1 0 0 qo20
98 - - B -- OUTPUT 0 1 0 0 qo21
29 - - E -- OUTPUT 0 1 0 0 qo22
14 - - C -- OUTPUT 0 1 0 0 qo23
78 - - F -- OUTPUT 0 1 0 0 qo24
100 - - A -- OUTPUT 0 1 0 0 qo25
88 - - D -- OUTPUT 0 1 0 0 qo26
97 - - C -- OUTPUT 0 1 0 0 qo27
21 - - D -- OUTPUT 0 1 0 0 qo28
89 - - D -- OUTPUT 0 1 0 0 qo29
23 - - D -- OUTPUT 0 1 0 0 qo30
48 - - - 24 OUTPUT 0 1 0 0 qo31
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: e:\frequent\latch_32.rpt
latch_32
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 4 - D 23 DFFE + 1 0 1 0 :98
- 6 - D 28 DFFE + 1 0 1 0 :99
- 6 - D 15 DFFE + 1 0 1 0 :100
- 4 - D 34 DFFE + 1 0 1 0 :101
- 1 - C 17 DFFE + 1 0 1 0 :102
- 8 - D 03 DFFE + 1 0 1 0 :103
- 8 - A 12 DFFE + 1 0 1 0 :104
- 8 - F 16 DFFE + 1 0 1 0 :105
- 4 - C 29 DFFE + 1 0 1 0 :106
- 6 - E 30 DFFE + 1 0 1 0 :107
- 5 - B 08 DFFE + 1 0 1 0 :108
- 6 - C 35 DFFE + 1 0 1 0 :109
- 2 - F 13 DFFE + 1 0 1 0 :110
- 5 - F 29 DFFE + 1 0 1 0 :111
- 1 - C 04 DFFE + 1 0 1 0 :112
- 3 - B 11 DFFE + 1 0 1 0 :113
- 4 - E 01 DFFE + 1 0 1 0 :114
- 1 - F 36 DFFE + 1 0 1 0 :115
- 4 - F 10 DFFE + 1 0 1 0 :116
- 6 - A 32 DFFE + 1 0 1 0 :117
- 4 - C 13 DFFE + 1 0 1 0 :118
- 1 - D 04 DFFE + 1 0 1 0 :119
- 1 - E 20 DFFE + 1 0 1 0 :120
- 1 - D 19 DFFE + 1 0 1 0 :121
- 6 - B 19 DFFE + 1 0 1 0 :122
- 1 - E 11 DFFE + 1 0 1 0 :123
- 6 - A 11 DFFE + 1 0 1 0 :124
- 1 - F 11 DFFE + 1 0 1 0 :125
- 2 - B 34 DFFE + 1 0 1 0 :126
- 7 - C 19 DFFE + 1 0 1 0 :127
- 8 - C 04 DFFE + 1 0 1 0 :128
- 2 - C 26 DFFE + 1 0 1 0 :129
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: e:\frequent\latch_32.rpt
latch_32
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 2/144( 1%) 3/ 72( 4%) 1/ 72( 1%) 2/16( 12%) 3/16( 18%) 0/16( 0%)
B: 1/144( 0%) 4/ 72( 5%) 2/ 72( 2%) 0/16( 0%) 4/16( 25%) 0/16( 0%)
C: 4/144( 2%) 4/ 72( 5%) 4/ 72( 5%) 2/16( 12%) 7/16( 43%) 0/16( 0%)
D: 4/144( 2%) 5/ 72( 6%) 4/ 72( 5%) 4/16( 25%) 6/16( 37%) 0/16( 0%)
E: 3/144( 2%) 3/ 72( 4%) 2/ 72( 2%) 3/16( 18%) 4/16( 25%) 0/16( 0%)
F: 4/144( 2%) 3/ 72( 4%) 4/ 72( 5%) 3/16( 18%) 6/16( 37%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
02: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
03: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
09: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
12: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
25: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
26: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
27: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
28: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
29: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
30: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
31: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
32: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
33: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
34: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
35: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
36: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: e:\frequent\latch_32.rpt
latch_32
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 32 load
Device-Specific Information: e:\frequent\latch_32.rpt
latch_32
** EQUATIONS **
din0 : INPUT;
din1 : INPUT;
din2 : INPUT;
din3 : INPUT;
din4 : INPUT;
din5 : INPUT;
din6 : INPUT;
din7 : INPUT;
din8 : INPUT;
din9 : INPUT;
din10 : INPUT;
din11 : INPUT;
din12 : INPUT;
din13 : INPUT;
din14 : INPUT;
din15 : INPUT;
din16 : INPUT;
din17 : INPUT;
din18 : INPUT;
din19 : INPUT;
din20 : INPUT;
din21 : INPUT;
din22 : INPUT;
din23 : INPUT;
din24 : INPUT;
din25 : INPUT;
din26 : INPUT;
din27 : INPUT;
din28 : INPUT;
din29 : INPUT;
din30 : INPUT;
din31 : INPUT;
load : INPUT;
-- Node name is 'qo0'
-- Equation name is 'qo0', type is output
qo0 = _LC2_C26;
-- Node name is 'qo1'
-- Equation name is 'qo1', type is output
qo1 = _LC8_C4;
-- Node name is 'qo2'
-- Equation name is 'qo2', type is output
qo2 = _LC7_C19;
-- Node name is 'qo3'
-- Equation name is 'qo3', type is output
qo3 = _LC2_B34;
-- Node name is 'qo4'
-- Equation name is 'qo4', type is output
qo4 = _LC1_F11;
-- Node name is 'qo5'
-- Equation name is 'qo5', type is output
qo5 = _LC6_A11;
-- Node name is 'qo6'
-- Equation name is 'qo6', type is output
qo6 = _LC1_E11;
-- Node name is 'qo7'
-- Equation name is 'qo7', type is output
qo7 = _LC6_B19;
-- Node name is 'qo8'
-- Equation name is 'qo8', type is output
qo8 = _LC1_D19;
-- Node name is 'qo9'
-- Equation name is 'qo9', type is output
qo9 = _LC1_E20;
-- Node name is 'qo10'
-- Equation name is 'qo10', type is output
qo10 = _LC1_D4;
-- Node name is 'qo11'
-- Equation name is 'qo11', type is output
qo11 = _LC4_C13;
-- Node name is 'qo12'
-- Equation name is 'qo12', type is output
qo12 = _LC6_A32;
-- Node name is 'qo13'
-- Equation name is 'qo13', type is output
qo13 = _LC4_F10;
-- Node name is 'qo14'
-- Equation name is 'qo14', type is output
qo14 = _LC1_F36;
-- Node name is 'qo15'
-- Equation name is 'qo15', type is output
qo15 = _LC4_E1;
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -