📄 latch_32.rpt
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Project Information e:\frequent\latch_32.rpt
MAX+plus II Compiler Report File
Version 10.2 07/10/2002
Compiled: 04/24/2007 11:18:12
Copyright (C) 1988-2002 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
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under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
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***** Project compilation was successful
** DEVICE SUMMARY **
Chip/ Input Output Bidir Memory Memory LCs
POF Device Pins Pins Pins Bits % Utilized LCs % Utilized
latch_32 EP1K30TC144-3 33 32 0 0 0 % 32 1 %
User Pins: 33 32 0
Device-Specific Information: e:\frequent\latch_32.rpt
latch_32
***** Logic for device 'latch_32' compiled without errors.
Device: EP1K30TC144-3
ACEX 1K Configuration Scheme: Passive Serial
Device Options:
User-Supplied Start-Up Clock = OFF
Auto-Restart Configuration on Frame Error = OFF
Release Clears Before Tri-States = OFF
Enable Chip_Wide Reset = OFF
Enable Chip-Wide Output Enable = OFF
Enable INIT_DONE Output = OFF
JTAG User Code = 7f
MultiVolt I/O = OFF
R R R R R R R R R R R R R R R R R R R R R
E E E E E E E E E E E E E E E E E E E E E
S S S S S S S S S S S V S S S S S S S S S S
d E E E E E E d E V d E E E E C E E E E d E E V E E E E d d
i R R R R R R i R C i R R R R C d d d R R R R i R R C R R R R i i
n V V V V G V V n V C n V V V G V I i i i G V V V V n V V C V V V V n n
3 E E E E N E E 1 E I 1 E E E N E N n n n N E E E E 2 E E I E E E E 2 2
0 D D D D D D D 4 D O 8 D D D D D T 3 4 2 D D D D D 1 D D O D D D D 6 5
--------------------------------------------------------------------------_
/ 144 142 140 138 136 134 132 130 128 126 124 122 120 118 116 114 112 110 |_
/ 143 141 139 137 135 133 131 129 127 125 123 121 119 117 115 113 111 109 |
#TCK | 1 108 | ^DATA0
^CONF_DONE | 2 107 | ^DCLK
^nCEO | 3 106 | ^nCE
#TDO | 4 105 | #TDI
VCCIO | 5 104 | GND
GND | 6 103 | VCCINT
din12 | 7 102 | din5
qo12 | 8 101 | qo5
qo3 | 9 100 | qo25
qo7 | 10 99 | qo16
din17 | 11 98 | qo21
qo0 | 12 97 | qo27
din27 | 13 96 | qo11
qo23 | 14 95 | qo1
GND | 15 94 | VCCIO
VCCINT | 16 93 | GND
qo20 | 17 92 | qo10
qo2 | 18 91 | din8
qo8 | 19 EP1K30TC144-3 90 | din10
din28 | 20 89 | qo29
qo28 | 21 88 | qo26
din31 | 22 87 | qo6
qo30 | 23 86 | qo15
VCCIO | 24 85 | VCCINT
GND | 25 84 | GND
qo9 | 26 83 | din22
din6 | 27 82 | qo4
din9 | 28 81 | qo19
qo22 | 29 80 | qo13
qo14 | 30 79 | din19
din24 | 31 78 | qo24
qo18 | 32 77 | ^MSEL0
din13 | 33 76 | ^MSEL1
#TMS | 34 75 | VCCINT
^nSTATUS | 35 74 | ^nCONFIG
RESERVED | 36 73 | RESERVED
| 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 _|
\ 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 |
\---------------------------------------------------------------------------
R R R G d R d R V R R q R V d G V d l d G G d R V d d R R G d R R R V q
E E E N i E i E C E E o E C i N C i o i N N i E C i i E E N i E E E C o
S S S D n S n S C S S 3 S C n D C n a n D D n S C n n S S D n S S S C 1
E E E 7 E 2 E I E E 1 E I 2 I 0 d 1 2 E I 1 1 E E 1 E E E I 7
R R R R 0 R O R R R N 3 N 9 R O 5 6 R R 1 R R R O
V V V V V V V V T T V V V V V V
E E E E E E E E E E E E E E
D D D D D D D D D D D D D D
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (2.5 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (2.5 volts).
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
$ = Pin has PCI I/O option enabled. Pin is neither '5.0 V'- nor '3.3 V'-tolerant.
Device-Specific Information: e:\frequent\latch_32.rpt
latch_32
** RESOURCE USAGE **
Logic Column Row
Array Interconnect Interconnect Clears/ External
Block Logic Cells Driven Driven Clocks Presets Interconnect
A11 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 1/22( 4%)
A12 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 1/22( 4%)
A32 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 1/22( 4%)
B8 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 1/22( 4%)
B11 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 1/22( 4%)
B19 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 1/22( 4%)
B34 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 1/22( 4%)
C4 2/ 8( 25%) 1/ 8( 12%) 1/ 8( 12%) 1/2 0/2 2/22( 9%)
C13 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 1/22( 4%)
C17 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 1/22( 4%)
C19 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 1/22( 4%)
C26 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 1/22( 4%)
C29 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 1/22( 4%)
C35 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 1/22( 4%)
D3 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 1/22( 4%)
D4 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 1/22( 4%)
D15 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 1/22( 4%)
D19 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 1/22( 4%)
D23 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 1/2 0/2 1/22( 4%)
D28 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 1/22( 4%)
D34 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 1/22( 4%)
E1 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 1/22( 4%)
E11 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 1/22( 4%)
E20 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 1/22( 4%)
E30 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 1/22( 4%)
F10 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 1/22( 4%)
F11 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 1/22( 4%)
F13 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 1/22( 4%)
F16 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 1/22( 4%)
F29 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 1/22( 4%)
F36 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 1/22( 4%)
Embedded Column Row
Array Embedded Interconnect Interconnect Read/ External
Block Cells Driven Driven Clocks Write Interconnect
Total dedicated input pins used: 6/6 (100%)
Total I/O pins used: 59/96 ( 61%)
Total logic cells used: 32/1728 ( 1%)
Total embedded cells used: 0/96 ( 0%)
Total EABs used: 0/6 ( 0%)
Average fan-in: 1.00/4 ( 25%)
Total fan-in: 32/6912 ( 0%)
Total input pins required: 33
Total input I/O cell registers required: 0
Total output pins required: 32
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 0
Total reserved pins required 0
Total logic cells required: 32
Total flipflops required: 32
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 0/1728 ( 0%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 EA 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Total(LC/EC)
A: 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 3/0
B: 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 4/0
C: 0 0 0 2 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 1 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 1 0 8/0
D: 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0 0 1 0 0 7/0
E: 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 4/0
F: 0 0 0 0 0 0 0 0 0 1 1 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 6/0
Total: 1 0 1 3 0 0 0 1 0 1 4 1 2 0 1 1 1 0 0 3 1 0 0 1 0 0 1 0 1 2 1 0 1 0 2 1 1 32/0
Device-Specific Information: e:\frequent\latch_32.rpt
latch_32
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
54 - - - -- INPUT ^ 0 0 0 1 din0
56 - - - -- INPUT ^ 0 0 0 1 din1
124 - - - -- INPUT ^ 0 0 0 1 din2
126 - - - -- INPUT ^ 0 0 0 1 din3
125 - - - -- INPUT ^ 0 0 0 1 din4
102 - - A -- INPUT ^ 0 0 0 1 din5
27 - - E -- INPUT ^ 0 0 0 1 din6
41 - - - 31 INPUT ^ 0 0 0 1 din7
91 - - D -- INPUT ^ 0 0 0 1 din8
28 - - E -- INPUT ^ 0 0 0 1 din9
90 - - D -- INPUT ^ 0 0 0 1 din10
67 - - - 08 INPUT ^ 0 0 0 1 din11
7 - - A -- INPUT ^ 0 0 0 1 din12
33 - - F -- INPUT ^ 0 0 0 1 din13
136 - - - 30 INPUT ^ 0 0 0 1 din14
62 - - - 12 INPUT ^ 0 0 0 1 din15
63 - - - 11 INPUT ^ 0 0 0 1 din16
11 - - C -- INPUT ^ 0 0 0 1 din17
133 - - - 28 INPUT ^ 0 0 0 1 din18
79 - - F -- INPUT ^ 0 0 0 1 din19
43 - - - 30 INPUT ^ 0 0 0 1 din20
118 - - - 09 INPUT ^ 0 0 0 1 din21
83 - - E -- INPUT ^ 0 0 0 1 din22
51 - - - 20 INPUT ^ 0 0 0 1 din23
31 - - F -- INPUT ^ 0 0 0 1 din24
109 - - - 01 INPUT ^ 0 0 0 1 din25
110 - - - 02 INPUT ^ 0 0 0 1 din26
13 - - C -- INPUT ^ 0 0 0 1 din27
20 - - D -- INPUT ^ 0 0 0 1 din28
59 - - - 16 INPUT ^ 0 0 0 1 din29
144 - - - 36 INPUT ^ 0 0 0 1 din30
22 - - D -- INPUT ^ 0 0 0 1 din31
55 - - - -- INPUT G ^ 0 0 0 0 load
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
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