📄 mcp2515.h
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#ifndef _LINUX_MCP2515_H#define _LINUX_MCP2515_H#include <linux/config.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/miscdevice.h>
#include <linux/sched.h>
#include <linux/delay.h>
#include <linux/poll.h>
#include <linux/spinlock.h>
#include <linux/irq.h>
#include <linux/delay.h>
#include <linux/vmalloc.h>#include <linux/ioctl.h>#include <linux/Def.h>#include <linux/2410.h>
#include <linux/spi.h>#include <asm/hardware.h>
#include <asm/arch/cpu_s3c2410.h>
/**************************************************************************/
/********************** *********************************/
/********************** MCP2510 Regrister *********************************/
/********************** *********************************/
/**************************************************************************/
/********************** TX ************************************************/
#define MCP2515REG_TXBnCTRL 0
#define MCP2515REG_TXBnSIDH 1
#define MCP2515REG_TXBnSIDL 2
#define MCP2515REG_TXBnEID8 3
#define MCP2515REG_TXBnEID0 4
#define MCP2515REG_TXBnDLC 5
#define MCP2515REG_TXBnD0 6
#define MCP2515REG_TXBnD1 7
#define MCP2515REG_TXBnD2 8
#define MCP2515REG_TXBnD3 9
#define MCP2515REG_TXBnD4 10
#define MCP2515REG_TXBnD5 11
#define MCP2515REG_TXBnD6 12
#define MCP2515REG_TXBnD7 13
#define MCP2515REG_CANSTAT 14
#define MCP2515REG_CANCTRL 15
#define MCP2515LREG_SIDH 0
#define MCP2515LREG_SIDL 1
#define MCP2515LREG_EID8 2
#define MCP2515LREG_EID0 3
/**TXBnCTRL(n=0~2) address**/
#define TXB0CTRL 0x30 //
#define TXB1CTRL 0x40 //
#define TXB2CTRL 0x50 //
/**define TXBnCTRL<7:0>**/
//#define TXB_TXBUFE_SET 0x80 //bit7
#define TXB_ABTF_SET 0x40 //bit6
#define TXB_MLOA_SET 0x20 //bit5
#define TXB_TXERR_SET 0x10 //bit4
#define TXB_TXREQ_SET 0x08 //bit3
//#define TXB_TXIE_SET 0x04 //bit2
#define TXB_TXP10_H_SET 0x03 //bit0,1 (1,1) high
#define TXB_TXP10_MH_SET 0x02 //bit0,1 (1,0) middle_high
#define TXB_TXP10_ML_SET 0x01 //bit0,1 (0,1) middle_low
#define TXB_TXP10_HL_SET 0x00 //bit0,1 (0,0) low
/**TXBnSIDH(n=0~2) address**/
#define TXB0SIDH 0x31 //bit<7:0>==sid<10:3>
#define TXB1SIDH 0x41 //
#define TXB2SIDH 0x51 //
/**TXBnSIDL(n=0~2) address:32h,42h,52h**/
//bit<7:5>==sid<2:0>
//bit4 undef
#define TXB_EXIDE_SET 0x0800 //bit3 EXIDE
//bit2 undef
//bit<1:0>==eid<17:16>
/**TXBnEID8(n=0~2) address:33h,43h,53h**/
//bit<7:0>==eid<15:8>
/**TXBnEID0(n=0~2) address:34h,44h,54h**/
//bit<7:0>==eid<7:0>
/**TXBnDLC(n=0~2) address:35h,45h,55h**/
//bit7 undef
#define TXB_RTR_SET 0x40 //bit6 RTR
//bit<5:4> undef
#define TXB_DLC_SET 0x07 //bit<3:0> data length=8
/**TXBnD0~7(n=0~2)**/
/**TXRTSCTRL address**/
#define TXRTSCTRL 0x0D
/********************** RX ************************************************/
/**RXBnCTRL address**/
#define RXB0CTRL 0x60
#define RXB1CTRL 0x70
/**define RXBnCTRL<7:0>**/
//bit7 undef
#define RXB_RXM1_SET 0x40 //bit6
#define RXB_RXM0_SET 0x20 //bit5
#define RXB_RX_ANY 0x60
#define RXB_RX_EXT 0x40
#define RXB_RX_STD 0x20
#define RXB_RX_STDEXT 0x00
//bit4 UNDEF
#define RXB_RXRTR_SET 0x08 //bit3
//RXB0
#define RXB_BUKT_SET 0x04 //bit2
#define RXB_BUKT_RO_SET 0x02 //bit1
#define RXB0_FILHIT0_SET 0x01 //bit0
//RXB1
#define RXB1_FILHIT2_SET 0x04 //bit2
#define RXB1_FILHIT1_SET 0x02 //bit1
#define RXB1_FILHIT0_SET 0x01 //bit0
/**RXBnSIDH(n=0,1) address**/
#define RXB0SIDH 0x61 //bit<7:0>==sid<10:3>
#define RXB1SIDH 0x71 //
/**RXBnSIDL(n=0,1) address:62h,72h**/
//bit<7:5>==sid<2:0>
#define RXB_SRR_SET 0X40 //bit6 SRR
#define RXB_IDE_SET 0x08 //bit3 IDE
//bit2 undef
//bit<1:0>==eid<17:16>
/**RXBnEID8(n=0,1) address:63h,73h**/
//bit<7:0>==eid<15:8>
/**RXBnEID0(n=0,1) address:64h,74h**/
//bit<7:0>==eid<7:0>
/**RXBnDLC(n=0,1) address:65h,75h**/
//bit7 undef
#define RXB_RTR_SET 0x40 //bit6 RTR
#define RXB_RB1_SET 0X20 //bit5 RB1
#define RXB_RB0_SET 0X10 //bit4 RB1
#define RXB_DLC_SET 0x0F //bit<3:0> data length=8
/**RXBnD0~7(n=0,1)**/
/**BFPCTRL address**/
#define BFPCTRL 0x0C
/********************** RX:(f*6)&(m*2) ************************************************/
#define RXF0SIDH 0
#define RXF0SIDL 1
#define RXF0EID8 2
#define RXF0EID0 3
#define RXF1SIDH 4
#define RXF1SIDL 5
#define RXF1EID8 6
#define RXF1EID0 7
#define RXF2SIDH 8
#define RXF2SIDL 9
#define RXF2EID8 10
#define RXF2EID0 11
#define RXF3SIDH 16
#define RXF3SIDL 17
#define RXF3EID8 18
#define RXF3EID0 19
#define RXF4SIDH 20
#define RXF4SIDL 21
#define RXF4EID8 22
#define RXF4EID0 23
#define RXF5SIDH 24
#define RXF5SIDL 25
#define RXF5EID8 26
#define RXF5EID0 27
#define RXB_RXF5 0x05
#define RXB_RXF4 0x04
#define RXB_RXF3 0x03
#define RXB_RXF2 0x02
#define RXB_RXF1 0x01
#define RXB_RXF0 0x00
/**RXFnSIDH(n=0~5)**/
//bit<7:0>==sid<10:3>
/**RXFnSIDL(n=0~5)**/
//bit<7:5>==sid<2:0>
//bit4 undef
#define RXF_EXIDE_SET 0x08 //bit3 EXIDE
//bit2 undef
//bit<1:0>==eid<17:16>
/**RXFnEID8(n=0~5)**/
//bit<7:0>==eid<15:8>
/**RXFnEID0(n=0,1)**/
//bit<7:0>==eid<7:0>
#define RXM0SIDH 0x20
#define RXM0SIDL 0x21
#define RXM0EID8 0x22
#define RXM0EID0 0x23
#define RXM1SIDH 0x24
#define RXM1SIDL 0x25
#define RXM1EID8 0x26
#define RXM1EID0 0x27
/*************************************** ERR_REG ********************************/
//address
#define TEC 0x1C
#define REC 0x1D
#define EFLG 0x2D
/**EFLG**/
#define EFLG_RX1OVR 0x80
#define EFLG_RX0OVR 0x40
#define EFLG_TXBO 0x20
#define EFLG_TXEP 0x10
#define EFLG_RXEP 0x08
#define EFLG_TXWAR 0x04
#define EFLG_RXWAR 0x02
#define EFLG_EWARN 0x01
/******************************* BIT_TIME REG ****************************************/
/**address**/
#define CNF3 0x28
#define CNF2 0x29
#define CNF1 0x2A
/**CNF1**/
//bit<7:6>
#define SJW1 0x00 //1*TQ
#define SJW2 0x40 //2*TQ
#define SJW3 0x80 //3*TQ
#define SJW4 0xC0 //4*TQ
//bit<5:0>
#define BRP1 0x00 //brp=2 x (BRP + 1)/FOSC
#define BRP2 0x01
#define BRP3 0x02
#define BRP4 0x03
#define BRP5 0x04
#define BRP6 0x05
#define BRP7 0x06
#define BRP8 0x07
/**CNF2**/
#define BTLMODE_SET 0x80 //bit7
//bit6 sample
#define SAMP1 0x00 //sample 1#define SAMP3 0x40 //sample 3//bit<5:3> PS1SEG
//bit<2:0> PRSEG
#define SEG1 0x00
#define SEG2 0x01
#define SEG3 0x02
#define SEG4 0x03
#define SEG5 0x04
#define SEG6 0x05
#define SEG7 0x06
#define SEG8 0x07 //seg=segn+1
/**CNF3**/
#define SOF_SET 0x80 //bit7
#define WALFIL_SET 0x60 //bit6
//bit<5:3> undef
//bit<2:0> PS2SEG
/*********************************INTERRUPT REG *****************************************/
/** address **/
#define CANINTE 0x2B
#define CANINTF 0x2C
/**CANINTE**/#define IVRIE 0x80 //bit7
#define WAKIE 0x40 //bit6
#define ERRIE 0x20 //bit5
#define TX2IE 0x10 //bit4
#define TX1IE 0x08 //bit3
#define TX0IE 0x04 //bit2
#define RX1IE 0x02 //bit1
#define RX0IE 0x01 //bit0
#define NO_IE 0x00 //interrupt disable
/**CANINTF**/
#define IVRINT 0x80
#define WAKINT 0x40
#define ERRINT 0x20
#define TX2INT 0x10
#define TX1INT 0x08
#define TX0INT 0x04
#define RX1INT 0x02
#define RX0INT 0x01
#define NO_INT 0x00 //no interrupt request
/************************** can_control REG******************************************/
/**CANCTRL**/
//bit<7:6> can working mode
#define MODE_NORMAL 0x00
#define MODE_SLEEP 0x20
#define MODE_LOOPBACK 0x40
#define MODE_LISTENONLY 0x60
#define MODE_CONFIG 0x80
#define CAN_ABORT_SET 0x10 //bit4
#define CAN_OSM_SET 0X08 //bit3
#define CLKEN 0x04 //bit2 clk_output enable
//bit<1:0>
#define CLK1 0x00
#define CLK2 0x01
#define CLK4 0x02
#define CLK8 0x03
/**CANSTAT**/
//bit<7:5> can working mode "read"
//bit4 undef
//bit<3:1>
#define STAT_READ_NO_INT 0x00
#define STAT_READ_ERR_INT 0x02
#define STAT_READ_WAK_INT 0x04
#define STAT_READ_TXB0_INT 0x06
#define STAT_READ_TXB1_INT 0x08
#define STAT_READ_TXB2_INT 0x0a
#define STAT_READ_RXB0_INT 0x0c
#define STAT_READ_RXB1_INT 0x0e
//bit0 undef
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