📄 simple_pll_3.mdl
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}
Block {
BlockType Terminator
Name "Terminator2"
Position [440, 130, 460, 150]
Orientation "down"
NamePlacement "alternate"
ShowName off
}
Block {
BlockType Reference
Name "Voltage Measurement"
Tag "PoWeRsYsTeMmEaSuReMeNt"
Ports [0, 1, 0, 0, 0, 2]
Position [725, 167, 755, 203]
ShowName off
AttributesFormatString "\\n"
DialogController "POWERSYS.PowerSysDialog"
SourceBlock "powerlib/Measurements/Voltage Measurement"
SourceType "Voltage Measurement"
ShowPortLabels "FromPortIcon"
SystemSampleTime "-1"
FunctionWithSeparateData off
RTWMemSecFuncInitTerm "Inherit from model"
RTWMemSecFuncExecute "Inherit from model"
RTWMemSecDataConstants "Inherit from model"
RTWMemSecDataInternal "Inherit from model"
RTWMemSecDataParameters "Inherit from model"
PhasorSimulation off
OutputType "Magnitude"
PSBequivalent "0"
Port {
PortNumber 1
Name "vco_contrl\n"
RTWStorageClass "Auto"
DataLoggingNameMode "SignalName"
}
}
Block {
BlockType Reference
Name "Voltage-Controlled\nOscillator1"
Ports [1, 1]
Position [490, 327, 580, 373]
Orientation "left"
FontName "Arial"
SourceBlock "commsynccomp2/Continuous-Time\nVCO"
SourceType "Continuous-Time VCO"
ShowPortLabels "FromPortIcon"
SystemSampleTime "-1"
FunctionWithSeparateData off
RTWMemSecFuncInitTerm "Inherit from model"
RTWMemSecFuncExecute "Inherit from model"
RTWMemSecDataConstants "Inherit from model"
RTWMemSecDataInternal "Inherit from model"
RTWMemSecDataParameters "Inherit from model"
Ac "1"
Fc "8*90e6"
Kc "8*20e6/5"
Ph "pi"
}
Block {
BlockType Constant
Name "c0\n"
Position [85, 195, 100, 215]
OutDataType "sfix(16)"
OutScaling "2^0"
}
Block {
BlockType Reference
Name "powergui"
Ports []
Position [15, 125, 75, 149]
UserDataPersistent on
FontSize 11
SourceBlock "powerlib/powergui"
SourceType "PSB option menu block"
ShowPortLabels "FromPortIcon"
SystemSampleTime "-1"
FunctionWithSeparateData off
RTWMemSecFuncInitTerm "Inherit from model"
RTWMemSecFuncExecute "Inherit from model"
RTWMemSecDataConstants "Inherit from model"
RTWMemSecDataInternal "Inherit from model"
RTWMemSecDataParameters "Inherit from model"
SimulationMode "Continuous"
SampleTime "50e-6"
echomessages off
RestoreLinks "warning"
x0status "blocks"
Frange "[0:2:500]"
Ylog off
Xlog on
ShowGrid off
save off
variable "ZData"
ZoomFFT on
StartTime "0.0"
cycles "1"
DisplayStyle "1"
fundamental "60"
FreqAxis off
MaxFrequency "1000"
frequencyindice "0"
frequencyindicesteady "1"
RmsSteady "1"
display off
Ts "0"
frequency "60"
methode off
HookPort off
Interpol off
SPID off
FunctionMessages off
}
Line {
SrcBlock "Logical\nOperator"
SrcPort 1
DstBlock "Reset Delay "
DstPort 1
}
Line {
SrcBlock "D Flip-Flop1"
SrcPort 1
Points [90, 0; 0, 90]
DstBlock "Logical\nOperator"
DstPort 1
}
Line {
SrcBlock "D Flip-Flop"
SrcPort 1
Points [90, 0; 0, -60]
DstBlock "Logical\nOperator"
DstPort 2
}
Line {
SrcBlock "Reset Delay "
SrcPort 1
Points [0, 0; -35, 0]
Branch {
Points [0, 110]
DstBlock "D Flip-Flop"
DstPort 3
}
Branch {
Points [0, -55]
DstBlock "D Flip-Flop1"
DstPort 3
}
}
Line {
SrcBlock "Make Square"
SrcPort 1
DstBlock "D Flip-Flop1"
DstPort 2
}
Line {
Name "clk_in"
Labels [0, 0; 1, 0]
SrcBlock "Make Square1"
SrcPort 1
Points [-105, 0]
DstBlock "Divide by N"
DstPort trigger
}
Line {
Name "clk_out"
Labels [0, 0; 2, 0]
SrcBlock "Divide by N"
SrcPort 1
Points [-55, 0; 0, -170]
DstBlock "D Flip-Flop"
DstPort 2
}
Line {
SrcBlock "8*100=800 MHz\n"
SrcPort 1
DstBlock "Divide by N"
DstPort 1
}
Line {
SrcBlock "c0\n"
SrcPort 1
Points [0, 0; 25, 0]
Branch {
DstBlock "D Flip-Flop"
DstPort 1
}
Branch {
Points [0, -165]
DstBlock "D Flip-Flop1"
DstPort 1
}
}
Line {
SrcBlock "D Flip-Flop"
SrcPort 2
Points [0, 0; 15, 0]
Branch {
Points [0, 35]
DstBlock "Delay Asymmetry"
DstPort 1
}
Branch {
Points [65, 0]
DstBlock "SW1"
DstPort 1
}
}
Line {
SrcBlock "Ref Osc\n100 MHz"
SrcPort 1
DstBlock "Make Square"
DstPort 1
}
Line {
SrcBlock "40 MHz Elliptic "
SrcPort 1
Points [20, 0; 0, 45]
DstBlock "SW2 "
DstPort 2
}
Line {
SrcBlock "Delay Asymmetry"
SrcPort 1
DstBlock "SW1"
DstPort 2
}
Line {
SrcBlock "Ideal Switch2"
SrcPort 1
DstBlock "Terminator2"
DstPort 1
}
Line {
SrcBlock "Ideal Switch4"
SrcPort 1
DstBlock "Terminator1"
DstPort 1
}
Line {
LineType "Connection"
SrcBlock "Ground (output)4"
SrcPort LConn1
Points [0, -40; 90, 0]
DstBlock "Ideal Switch2"
DstPort LConn1
}
Line {
SrcBlock "D Flip-Flop1"
SrcPort 2
Points [115, 0; 0, -50; 100, 0]
DstBlock "Ideal Switch2"
DstPort 1
}
Line {
Name "vco_contrl\n"
SrcBlock "Voltage Measurement"
SrcPort 1
Points [20, 0]
Branch {
DstBlock "40 MHz Elliptic "
DstPort 1
}
Branch {
Points [0, 45]
DstBlock "SW2 "
DstPort 1
}
}
Line {
LineType "Connection"
SrcBlock "DC Voltage Source1"
SrcPort RConn1
Points [-20, 0]
DstBlock "Ideal Switch4"
DstPort LConn1
}
Line {
SrcBlock "SW1"
SrcPort 1
Points [15, 0]
DstBlock "Ideal Switch4"
DstPort 1
}
Line {
LineType "Connection"
Points [590, 175; 60, 0]
Branch {
ConnectType "SRC_DEST"
SrcBlock "1e3 ohm3"
SrcPort RConn1
Points [5, 0; 10, 0]
}
Branch {
ConnectType "SRC_DEST"
SrcBlock "1.59e-10 F"
SrcPort RConn1
Points [0, -15]
}
Branch {
ConnectType "DEST_SRC"
DstBlock "Voltage Measurement"
DstPort LConn1
}
Branch {
ConnectType "DEST_DEST"
SrcBlock "1.59e-10 F1"
SrcPort RConn1
Points [0, -20]
}
}
Line {
LineType "Connection"
SrcBlock "Ideal Switch2"
SrcPort RConn1
Points [0, 55]
Branch {
ConnectType "DEST_DEST"
SrcBlock "Ideal Switch4"
SrcPort RConn1
Points [0, -10; 70, 0]
}
Branch {
ConnectType "DEST_SRC"
DstBlock "1e3 ohm3"
DstPort LConn1
}
}
Line {
LineType "Connection"
SrcBlock "1.59e-10 F"
SrcPort LConn1
Points [0, 0; 0, 20]
Branch {
ConnectType "DEST_SRC"
Points [30, 0]
Branch {
ConnectType "DEST_SRC"
Points [30, 0]
Branch {
ConnectType "DEST_SRC"
DstBlock "1.59e-10 F1"
DstPort LConn1
}
Branch {
ConnectType "DEST_SRC"
Points [45, 0; 0, -100]
DstBlock "Voltage Measurement"
DstPort LConn2
}
}
Branch {
ConnectType "DEST_SRC"
DstBlock "G2"
DstPort LConn1
}
}
Branch {
ConnectType "DEST_SRC"
DstBlock "DC Voltage Source1"
DstPort LConn1
}
}
Line {
SrcBlock "Voltage-Controlled\nOscillator1"
SrcPort 1
Points [-35, 0]
Branch {
DstBlock "Make Square1"
DstPort 1
}
Branch {
Points [0, 80]
DstBlock "RF Spectum Analyzer (Image Reject)"
DstPort 1
}
}
Line {
SrcBlock "SW2 "
SrcPort 1
Points [0, 65]
Branch {
DstBlock "Voltage-Controlled\nOscillator1"
DstPort 1
}
Branch {
DstBlock "Scope"
DstPort 1
}
}
Annotation {
Name " [a,b]=ellip(5,1,60,2*pi*40e6,'s');"
Position [823, 153]
}
Annotation {
Name "This model demonstrates that chaotic behavior can occur in feedback systems \nwith non-linear components. \n\nRun the model with SW1=up SW2=left. Note the \"perfection\" in the \nspectrum result. Then change SW1=down. This introduces a small delay \nin one path of the D FF phase detector. Run the model. This asymmetery \ninduces a (mildely) chaotic behavior (noise) plus the reference sidebands \nin the spectrum. Then change SW2=right. This filters the signal from the \nphase detector therefore removing the periodic component that produces \nthe sidebands. However the noise due to the chaotic process is still present \nin the passband of the filter. "
Position [568, 77]
HorizontalAlignment "left"
}
Annotation {
Name "270"
Position [534, 196]
}
Annotation {
Name "150p"
Position [556, 220]
}
Annotation {
Name "47"
Position [559, 247]
}
Annotation {
Name "47p"
Position [627, 222]
}
}
}
MatData {
NumRecords 1
DataRecord {
Tag DataTag0
Data " %)30 . , 8 ( ! % \" 0 0 "
}
}
# Finite State Machines
#
# Stateflow Version 6.7 (R2007b) dated Aug 7 2007, 16:48:14
#
#
Stateflow {
machine {
id 1
name "simple_pll_3"
created "16-Jun-2006 07:21:44"
isLibrary 0
firstTarget 2
sfVersion 67014000.000001
}
target {
id 2
name "sfun"
description "Default Simulink S-Function Target."
machine 1
linkNode [1 0 3]
}
target {
id 3
name "rtw"
codeFlags " comments=1 statebitsets=1 databitsets=1 emitlogicalops=1 elseifdetection=1 constantfolding=1 redundantloadelimination=0 preservenames=0 preservenameswithparent=0 exportcharts=0"
machine 1
linkNode [1 2 0]
}
}
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