📄 pll_frequencey_synthesis.mdl
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}
Block {
BlockType SubSystem
Name "Calculate single tone \nfrequency"
Ports [1, 1, 0, 1]
Position [90, 73, 165, 127]
TreatAsAtomicUnit on
MinAlgLoopOccurrences off
PropExecContextOutsideSubsystem off
RTWSystemCode "Auto"
FunctionWithSeparateData off
Opaque off
RequestExecContextInheritance off
MaskHideContents off
System {
Name "Calculate single tone \nfrequency"
Location [99, 524, 780, 705]
Open off
ModelBrowserVisibility off
ModelBrowserWidth 200
ScreenColor "white"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "A4"
PaperUnits "centimeters"
TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000]
TiledPageScale 1
ShowPageBoundaries off
ZoomFactor "100"
Block {
BlockType Inport
Name "Time"
Position [40, 63, 70, 77]
IconDisplay "Port number"
OutDataType "sfix(16)"
OutScaling "2^0"
Port {
PortNumber 1
Name "Time of current edge"
RTWStorageClass "Auto"
DataLoggingNameMode "SignalName"
}
}
Block {
BlockType TriggerPort
Name "Trigger"
Ports []
Position [75, 110, 95, 130]
ZeroCross off
}
Block {
BlockType Constant
Name "Constant"
Position [270, 110, 300, 140]
ShowName off
Value "0"
OutDataType "sfix(16)"
OutScaling "2^0"
}
Block {
BlockType Memory
Name "Memory"
Position [125, 55, 155, 85]
InheritSampleTime on
Port {
PortNumber 1
Name "Time of previous edge"
RTWStorageClass "Auto"
DataLoggingNameMode "SignalName"
}
}
Block {
BlockType Product
Name "Product"
Ports [1, 1]
Position [375, 24, 405, 56]
ShowName off
Inputs "/"
OutDataType "sfix(16)"
OutScaling "2^0"
RndMeth "Floor"
Port {
PortNumber 1
Name "Frequency"
RTWStorageClass "Auto"
DataLoggingNameMode "SignalName"
}
}
Block {
BlockType RelationalOperator
Name "Relational\nOperator"
Position [365, 102, 395, 133]
ShowName off
Operator "~="
Port {
PortNumber 1
Name "Gating signal"
RTWStorageClass "Auto"
DataLoggingNameMode "SignalName"
}
}
Block {
BlockType Product
Name "Set to Zero\nif previous time\nwas zero"
Ports [2, 1]
Position [535, 32, 565, 63]
OutDataType "sfix(16)"
OutScaling "2^0"
RndMeth "Floor"
}
Block {
BlockType Sum
Name "Sum"
Ports [2, 1]
Position [305, 30, 325, 50]
ShowName off
IconShape "round"
Inputs "|+-"
OutDataType "sfix(16)"
OutScaling "2^0"
Port {
PortNumber 1
Name "Period"
RTWStorageClass "Auto"
DataLoggingNameMode "SignalName"
}
}
Block {
BlockType Outport
Name "Freq"
Position [615, 43, 645, 57]
IconDisplay "Port number"
OutDataType "sfix(16)"
OutScaling "2^0"
InitialOutput "0"
}
Line {
Name "Gating signal"
Labels [2, 0]
SrcBlock "Relational\nOperator"
SrcPort 1
Points [55, 0; 0, -65]
DstBlock "Set to Zero\nif previous time\nwas zero"
DstPort 2
}
Line {
SrcBlock "Constant"
SrcPort 1
DstBlock "Relational\nOperator"
DstPort 2
}
Line {
SrcBlock "Set to Zero\nif previous time\nwas zero"
SrcPort 1
DstBlock "Freq"
DstPort 1
}
Line {
Name "Time of previous edge"
Labels [1, 1]
SrcBlock "Memory"
SrcPort 1
Points [155, 0]
Branch {
Points [0, 40]
DstBlock "Relational\nOperator"
DstPort 1
}
Branch {
DstBlock "Sum"
DstPort 2
}
}
Line {
Name "Frequency"
Labels [1, 0]
SrcBlock "Product"
SrcPort 1
DstBlock "Set to Zero\nif previous time\nwas zero"
DstPort 1
}
Line {
Name "Period"
Labels [-1, 1]
SrcBlock "Sum"
SrcPort 1
DstBlock "Product"
DstPort 1
}
Line {
Name "Time of current edge"
SrcBlock "Time"
SrcPort 1
Points [35, 0]
Branch {
DstBlock "Memory"
DstPort 1
}
Branch {
Labels [2, 0]
Points [0, -30]
DstBlock "Sum"
DstPort 1
}
}
Annotation {
Name "Ensure frequency calculation\nonly for full period"
Position [507, 151]
}
}
}
Block {
BlockType Clock
Name "Clock"
Position [25, 90, 45, 110]
Decimation "1"
}
Block {
BlockType Outport
Name "Out1"
Position [190, 93, 220, 107]
IconDisplay "Port number"
OutDataType "sfix(16)"
OutScaling "2^0"
}
Line {
SrcBlock "Calculate single tone \nfrequency"
SrcPort 1
DstBlock "Out1"
DstPort 1
}
Line {
SrcBlock "Clock"
SrcPort 1
DstBlock "Calculate single tone \nfrequency"
DstPort 1
}
Line {
SrcBlock "In1"
SrcPort 1
DstBlock "Calculate single tone \nfrequency"
DstPort trigger
}
}
}
Block {
BlockType Scope
Name "Frequency-Divided\nReference Signal"
Ports [1]
Position [375, 59, 405, 91]
Floating off
Location [686, 384, 1010, 623]
Open off
NumInputPorts "1"
List {
ListType AxesTitles
axes1 "%<SignalLabel>"
}
TimeRange "2e-007"
YMin "-1"
YMax "2"
SaveName "ScopeData3"
DataFormat "StructureWithTime"
SampleTime "0"
}
Block {
BlockType Scope
Name "Frequency-Divided\nSynthesized Signal"
Ports [1]
Position [410, 199, 440, 231]
Floating off
Location [352, 385, 676, 624]
Open off
NumInputPorts "1"
List {
ListType AxesTitles
axes1 "%<SignalLabel>"
}
TimeRange "2e-007"
YMin "-1"
YMax "2"
SaveName "ScopeData4"
DataFormat "StructureWithTime"
SampleTime "0"
}
Block {
BlockType Gain
Name "Gain"
Position [565, 135, 595, 165]
Gain "(synFr*synN/synM - synFq) * 2 / synSen"
ParameterDataType "sfix(16)"
ParameterScaling "2^0"
OutDataType "sfix(16)"
OutScaling "2^0"
}
Block {
BlockType Reference
Name "Info"
Ports []
Position [172, 289, 223, 339]
BackgroundColor "cyan"
ShowName off
SourceBlock "commblksprivate/Info"
SourceType ""
ShowPortLabels "FromPortIcon"
SystemSampleTime "-1"
FunctionWithSeparateData off
RTWMemSecFuncInitTerm "Inherit from model"
RTWMemSecFuncExecute "Inherit from model"
RTWMemSecDataConstants "Inherit from model"
RTWMemSecDataInternal "Inherit from model"
RTWMemSecDataParameters "Inherit from model"
}
Block {
BlockType Logic
Name "Phase\nDetector"
Ports [2, 1]
Position [375, 132, 405, 163]
Operator "XOR"
}
Block {
BlockType Scope
Name "Phase Detector\nOutput"
Ports [1]
Position [475, 59, 505, 91]
Floating off
Location [18, 385, 342, 625]
Open off
NumInputPorts "1"
List {
ListType AxesTitles
axes1 "%<SignalLabel>"
}
TimeRange "2e-007"
YMin "-1"
YMax "2"
SaveName "ScopeData5"
DataFormat "StructureWithTime"
SampleTime "0"
}
Block {
BlockType DiscretePulseGenerator
Name "Pulse\nGenerator"
Ports [0, 1]
Position [140, 125, 170, 155]
PulseType "Time based"
Period "1/synFr"
PulseWidth "50"
}
Block {
BlockType Scope
Name "Reference\nSignal"
Ports [1]
Position [225, 199, 255, 231]
Floating off
Location [682, 60, 1006, 300]
Open off
NumInputPorts "1"
List {
ListType AxesTitles
axes1 "%<SignalLabel>"
}
TimeRange "1e-007"
YMin "-1"
YMax "2"
DataFormat "StructureWithTime"
SampleTime "0"
}
Block {
BlockType Scope
Name "Synthesized\nSignal"
Ports [1]
Position [830, 134, 860, 166]
Floating off
Location [350, 59, 674, 300]
Open off
NumInputPorts "1"
ZoomMode "xonly"
List {
ListType AxesTitles
axes1 "%<SignalLabel>"
}
TimeRange "5e-008"
YMin "-1"
YMax "2"
SaveName "ScopeData2"
DataFormat "StructureWithTime"
MaxDataPoints "50000"
SampleTime "0"
}
Block {
BlockType Display
Name "Synthesized Frequency\nin Hz"
Ports [1]
Position [775, 320, 865, 350]
Decimation "1"
Lockdown off
}
Block {
BlockType Reference
Name "Voltage-Controlled\nOscillator"
Ports [1, 1]
Position [635, 128, 700, 172]
ShowName off
SourceBlock "commsynccomp2/Continuous-Time\nVCO"
SourceType "Continuous-Time VCO"
ShowPortLabels "FromPortIcon"
SystemSampleTime "-1"
FunctionWithSeparateData off
RTWMemSecFuncInitTerm "Inherit from model"
RTWMemSecFuncExecute "Inherit from model"
RTWMemSecDataConstants "Inherit from model"
RTWMemSecDataInternal "Inherit from model"
RTWMemSecDataParameters "Inherit from model"
Ac "1"
Fc "synFq"
Kc "synSen"
Ph "0"
}
Line {
SrcBlock "Pulse\nGenerator"
SrcPort 1
Points [20, 0]
Branch {
Points [0, 75]
DstBlock "Reference\nSignal"
DstPort 1
}
Branch {
DstBlock "Frequency Divider"
DstPort 1
}
}
Line {
SrcBlock "Phase\nDetector"
SrcPort 1
Points [40, 0]
Branch {
DstBlock "Analog\nFilter Design"
DstPort 1
}
Branch {
Points [0, -75]
DstBlock "Phase Detector\nOutput"
DstPort 1
}
}
Line {
SrcBlock "Gain"
SrcPort 1
Points [15, 0]
Branch {
DstBlock "Voltage-Controlled\nOscillator"
DstPort 1
}
Branch {
Points [0, -75]
DstBlock "Control\nSignal"
DstPort 1
}
}
Line {
SrcBlock "Voltage-Controlled\nOscillator"
SrcPort 1
DstBlock "Convert to\nSquare Wave"
DstPort 1
}
Line {
SrcBlock "Convert to\nSquare Wave"
SrcPort 1
Points [15, 0]
Branch {
DstBlock "Synthesized\nSignal"
DstPort 1
}
Branch {
Points [0, 115; -170, 0]
Branch {
DstBlock "Frequency Divider1"
DstPort 1
}
Branch {
Points [0, 70]
DstBlock "Frequency of\nsingle tone"
DstPort 1
}
}
}
Line {
SrcBlock "Frequency Divider"
SrcPort 1
Points [10, 0]
Branch {
DstBlock "Phase\nDetector"
DstPort 1
}
Branch {
Points [0, -65]
DstBlock "Frequency-Divided\nReference Signal"
DstPort 1
}
}
Line {
SrcBlock "Frequency Divider1"
SrcPort 1
Points [-140, 0; 0, -50]
Branch {
DstBlock "Phase\nDetector"
DstPort 2
}
Branch {
DstBlock "Frequency-Divided\nSynthesized Signal"
DstPort 1
}
}
Line {
SrcBlock "Analog\nFilter Design"
SrcPort 1
DstBlock "Gain"
DstPort 1
}
Line {
SrcBlock "Frequency of\nsingle tone"
SrcPort 1
DstBlock "Synthesized Frequency\nin Hz"
DstPort 1
}
}
}
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