5402.rpt

TI公司的DSP TMS320VC5402开发板的全套资料

s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell


Device-Specific Information:            e:\mydsp\dsp375\cpld\5402_gdf\5402.rpt
5402

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'A':

                   Logic cells placed in LAB 'A'
        +--------- LC2 INT0
        | +------- LC3 INT1
        | | +----- LC16 MEMRD
        | | | +--- LC15 MEMWR
        | | | | +- LC1 RAMCS
        | | | | | 
        | | | | |   Other LABs fed by signals
        | | | | |   that feed LAB 'A'
LC      | | | | | | A B |     Logic cells that feed LAB 'A':

Pin
6    -> - - - - * | * - | <-- DS
19   -> * - - - - | * - | <-- IRQ
3    -> - - * * - | * - | <-- MSTRB
37   -> - - * * - | * * | <-- RW
33   -> - * - - - | * - | <-- USBINT


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:            e:\mydsp\dsp375\cpld\5402_gdf\5402.rpt
5402

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'B':

                       Logic cells placed in LAB 'B'
        +------------- LC29 IORD
        | +----------- LC27 IOWR
        | | +--------- LC21 KEYOE
        | | | +------- LC28 LCDCS
        | | | | +----- LC24 NETCS
        | | | | | +--- LC18 NPS
        | | | | | | +- LC23 USBCS
        | | | | | | | 
        | | | | | | |   Other LABs fed by signals
        | | | | | | |   that feed LAB 'B'
LC      | | | | | | | | A B |     Logic cells that feed LAB 'B':

Pin
13   -> - - * * * - * | - * | <-- A12
12   -> - - * * * - * | - * | <-- A13
10   -> - - * * * - * | - * | <-- A14
2    -> * * * - - - - | - * | <-- IOSTRB
5    -> - - * * * - * | - * | <-- IS
8    -> - - - - - * - | - * | <-- PS
37   -> * * - - - - - | * * | <-- RW


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:            e:\mydsp\dsp375\cpld\5402_gdf\5402.rpt
5402

** EQUATIONS **

A12      : INPUT;
A13      : INPUT;
A14      : INPUT;
DS       : INPUT;
IOSTRB   : INPUT;
IRQ      : INPUT;
IS       : INPUT;
MSTRB    : INPUT;
PS       : INPUT;
RW       : INPUT;
USBINT   : INPUT;

-- Node name is 'INT0' 
-- Equation name is 'INT0', location is LC002, type is output.
 INT0    = LCELL(!IRQ $  GND);

-- Node name is 'INT1' 
-- Equation name is 'INT1', location is LC003, type is output.
 INT1    = LCELL( USBINT $  GND);

-- Node name is 'IORD' 
-- Equation name is 'IORD', location is LC029, type is output.
 IORD    = LCELL( _EQ001 $  VCC);
  _EQ001 = !IOSTRB &  RW;

-- Node name is 'IOWR' 
-- Equation name is 'IOWR', location is LC027, type is output.
 IOWR    = LCELL( _EQ002 $  VCC);
  _EQ002 = !IOSTRB & !RW;

-- Node name is 'KEYOE' 
-- Equation name is 'KEYOE', location is LC021, type is output.
 KEYOE   = LCELL( _EQ003 $  VCC);
  _EQ003 = !A12 & !A13 & !A14 & !IOSTRB & !IS;

-- Node name is 'LCDCS' 
-- Equation name is 'LCDCS', location is LC028, type is output.
 LCDCS   = LCELL( _EQ004 $  VCC);
  _EQ004 =  A12 &  A13 & !A14 & !IS;

-- Node name is 'MEMRD' 
-- Equation name is 'MEMRD', location is LC016, type is output.
 MEMRD   = LCELL( _EQ005 $  VCC);
  _EQ005 = !MSTRB &  RW;

-- Node name is 'MEMWR' 
-- Equation name is 'MEMWR', location is LC015, type is output.
 MEMWR   = LCELL( _EQ006 $  VCC);
  _EQ006 = !MSTRB & !RW;

-- Node name is 'NETCS' 
-- Equation name is 'NETCS', location is LC024, type is output.
 NETCS   = LCELL( _EQ007 $  VCC);
  _EQ007 = !A12 &  A13 & !A14 & !IS;

-- Node name is 'NPS' 
-- Equation name is 'NPS', location is LC018, type is output.
 NPS     = LCELL(!PS $  GND);

-- Node name is 'RAMCS' 
-- Equation name is 'RAMCS', location is LC001, type is output.
 RAMCS   = LCELL( DS $  GND);

-- Node name is 'USBCS' 
-- Equation name is 'USBCS', location is LC023, type is output.
 USBCS   = LCELL( _EQ008 $  VCC);
  _EQ008 =  A12 & !A13 & !A14 & !IS;



--     Shareable expanders that are duplicated in multiple LABs:
--     (none)




Project Information                     e:\mydsp\dsp375\cpld\5402_gdf\5402.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Standard

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'MAX3000A' family

      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      PARALLEL_EXPANDERS                  = off
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SOFT_BUFFER_INSERTION               = on
      SUBFACTOR_EXTRACTION                = on
      TURBO_BIT                           = on
      XOR_SYNTHESIS                       = on
      IGNORE_SOFT_BUFFERS                 = off
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      One-Hot State Machine Encoding      = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = on

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:00
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:01
   --------------------------             --------
   Total Time                             00:00:01


Memory Allocated
-----------------

Peak memory allocated during compilation  = 3,096K