📄 5402.rpt
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Project Information e:\mydsp\dsp375\cpld\5402_gdf\5402.rpt
MAX+plus II Compiler Report File
Version 10.2 07/10/2002
Compiled: 05/02/2006 20:10:52
Copyright (C) 1988-2002 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was successful
** DEVICE SUMMARY **
Chip/ Input Output Bidir Shareable
POF Device Pins Pins Pins LCs Expanders % Utilized
5402 EPM3032ATC44-10 11 12 0 12 0 37 %
User Pins: 11 12 0
Project Information e:\mydsp\dsp375\cpld\5402_gdf\5402.rpt
** PIN/LOCATION/CHIP ASSIGNMENTS **
Actual
User Assignments
Assignments (if different) Node Name
5402@13 A12
5402@12 A13
5402@10 A14
5402@6 DS
5402@43 INT0
5402@44 INT1
5402@21 IORD
5402@2 IOSTRB
5402@23 IOWR
5402@19 IRQ
5402@5 IS
5402@31 KEYOE
5402@22 LCDCS
5402@15 MEMRD
5402@14 MEMWR
5402@3 MSTRB
5402@27 NETCS
5402@34 NPS
5402@8 PS
5402@42 RAMCS
5402@37 RW
5402@28 USBCS
5402@33 USBINT
Project Information e:\mydsp\dsp375\cpld\5402_gdf\5402.rpt
** FILE HIERARCHY **
|74138:1|
|7404:47|
|7404:51|
|7404:50|
|7404:49|
Device-Specific Information: e:\mydsp\dsp375\cpld\5402_gdf\5402.rpt
5402
***** Logic for device '5402' compiled without errors.
Device: EPM3032ATC44-10
Device Options:
Turbo Bit = ON
Security Bit = OFF
Enable JTAG Support = ON
User Code = ffffffff
MultiVolt I/O = OFF
R
E
V S
R C E
I I A C R
N N M I G G G G V N
T T C N N N N R N E P
1 0 S T D D D W D D S
-----------------------------------_
/ 44 43 42 41 40 39 38 37 36 35 34 |
#TDI | 1 33 | USBINT
IOSTRB | 2 32 | #TDO
MSTRB | 3 31 | KEYOE
GND | 4 30 | GND
IS | 5 29 | VCCIO
DS | 6 EPM3032ATC44-10 28 | USBCS
#TMS | 7 27 | NETCS
PS | 8 26 | #TCK
VCCIO | 9 25 | RESERVED
A14 | 10 24 | GND
GND | 11 23 | IOWR
|_ 12 13 14 15 16 17 18 19 20 21 22 _|
------------------------------------
A A M M G V R I R I L
1 1 E E N C E R E O C
3 2 M M D C S Q S R D
W R I E E D C
R D N R R S
T V V
E E
D D
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (3.3 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (3.3 volts).
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
Device-Specific Information: e:\mydsp\dsp375\cpld\5402_gdf\5402.rpt
5402
** RESOURCE USAGE **
Shareable External
Logic Array Block Logic Cells I/O Pins Expanders Interconnect
A: LC1 - LC16 5/16( 31%) 15/15(100%) 0/16( 0%) 5/36( 13%)
B: LC17 - LC32 7/16( 43%) 11/15( 73%) 0/16( 0%) 7/36( 19%)
Total dedicated input pins used: 1/4 ( 25%)
Total I/O pins used: 26/30 ( 86%)
Total logic cells used: 12/32 ( 37%)
Total shareable expanders used: 0/32 ( 0%)
Total Turbo logic cells used: 12/32 ( 37%)
Total shareable expanders not available (n/a): 0/32 ( 0%)
Average fan-in: 2.41
Total fan-in: 29
Total input pins required: 11
Total output pins required: 12
Total bidirectional pins required: 0
Total reserved pins required 4
Total logic cells required: 12
Total flipflops required: 0
Total product terms required: 12
Total logic cells lending parallel expanders: 0
Total shareable expanders in database: 0
Synthesized logic cells: 0/ 32 ( 0%)
Device-Specific Information: e:\mydsp\dsp375\cpld\5402_gdf\5402.rpt
5402
** INPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
13 (14) (A) INPUT 0 0 0 0 0 4 0 A12
12 (13) (A) INPUT 0 0 0 0 0 4 0 A13
10 (11) (A) INPUT 0 0 0 0 0 4 0 A14
6 (8) (A) INPUT 0 0 0 0 0 1 0 DS
2 (5) (A) INPUT 0 0 0 0 0 3 0 IOSTRB
19 (31) (B) INPUT 0 0 0 0 0 1 0 IRQ
5 (7) (A) INPUT 0 0 0 0 0 4 0 IS
3 (6) (A) INPUT 0 0 0 0 0 2 0 MSTRB
8 (10) (A) INPUT 0 0 0 0 0 1 0 PS
37 - - INPUT 0 0 0 0 0 4 0 RW
33 (19) (B) INPUT 0 0 0 0 0 1 0 USBINT
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: e:\mydsp\dsp375\cpld\5402_gdf\5402.rpt
5402
** OUTPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
43 2 A OUTPUT t 0 0 0 1 0 0 0 INT0
44 3 A OUTPUT t 0 0 0 1 0 0 0 INT1
21 29 B OUTPUT t 0 0 0 2 0 0 0 IORD
23 27 B OUTPUT t 0 0 0 2 0 0 0 IOWR
31 21 B OUTPUT t 0 0 0 5 0 0 0 KEYOE
22 28 B OUTPUT t 0 0 0 4 0 0 0 LCDCS
15 16 A OUTPUT t 0 0 0 2 0 0 0 MEMRD
14 15 A OUTPUT t 0 0 0 2 0 0 0 MEMWR
27 24 B OUTPUT t 0 0 0 4 0 0 0 NETCS
34 18 B OUTPUT t 0 0 0 1 0 0 0 NPS
42 1 A OUTPUT t 0 0 0 1 0 0 0 RAMCS
28 23 B OUTPUT t 0 0 0 4 0 0 0 USBCS
Code:
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