palladium.c

Freescale MCF5445evb 参考测试代码

/*
 * File:        sysinit.c
 * Purpose:     Verdi Reset Configuration
 *
 * Notes:
 *
 */

#include "common.h"
#include "uart/uart.h"

/********************************************************************/

static void platform_fbcs_init(void);
static void platform_sdramc_init(void);

/********************************************************************/
void
platform_startup (void)
{
    /* Enable the proper UART pins */
    switch (TERMINAL_PORT)
    {
        case 0:
        default:
            MCF_PORT_PAR_UART |= 0
                | MCF_PORT_PAR_UART_U0RXD_U0RXD
                | MCF_PORT_PAR_UART_U0TXD_U0TXD;
    }
    /* Enable the default UART terminal port */
    uart_init(TERMINAL_PORT, SYS_CLK_KHZ, TERMINAL_BAUD, 0);

    /* Initialize the Flexbus */
    platform_fbcs_init();

    /* Initialize the SDRAM controller */
    platform_sdramc_init();
}
/********************************************************************/
static void
platform_fbcs_init (void)
{
    /* Boot SRAM connected to FBCS0 */
    MCF_FBCS0_CSAR = MCF_FBCS_CSAR_BA(BOOT_SRAM_ADDRESS);
    MCF_FBCS0_CSCR = 0
        | MCF_FBCS_CSCR_PS_32
        | MCF_FBCS_CSCR_BEM
        | MCF_FBCS_CSCR_AA
        | MCF_FBCS_CSCR_WS(7);
    MCF_FBCS0_CSMR = 0
        | MCF_FBCS_CSMR_BAM_32M
        | MCF_FBCS_CSMR_V;
}
/********************************************************************/
static void
platform_sdramc_init (void)
{

    /*
     * Check to see if the SDRAM has already been initialized
     * by a run control tool
     */
//  if (!(MCF_SDRAMC_SDCR & MCF_SDRAMC_SDCR_REF))
//  {

        /* SDRAM chip select initialization */

        /* Initialize SDRAM chip select */
        MCF_SDRAMC_SDCS0 = (0
            | MCF_SDRAMC_SDCS_BA(SDRAM_ADDRESS)
            | MCF_SDRAMC_SDCS_CSSZ(MCF_SDRAMC_SDCS_CSSZ_32MBYTE)
            );


        /*
         * Basic configuration and initialization
         */

#ifdef PALLADIUM

        MCF_SDRAMC_SDCFG1 = 0x33633F30;
        MCF_SDRAMC_SDCFG2 = 0x34470000;

        /* Not sure if this is really the correct refresh count for palladium.
           Because of the low clock speed we would need to refresh just about
           every clock to be completely correct, but that isn't really practical */

        MCF_SDRAMC_SDCR = (0
            | MCF_SDRAMC_SDCR_MODE_EN
            | MCF_SDRAMC_SDCR_CKE
            | MCF_SDRAMC_SDCR_DDR
            | MCF_SDRAMC_SDCR_MUX(0)
            | MCF_SDRAMC_SDCR_RCNT(9)
            | MCF_SDRAMC_SDCR_PS_16
            | MCF_SDRAMC_SDCR_IPALL
            );

#else

        MCF_SDRAMC_SDCFG1 = (0
            | MCF_SDRAMC_SDCFG1_SRD2RW(7)
            | MCF_SDRAMC_SDCFG1_SWT2RD(SDRAM_TWR + 1)
            | MCF_SDRAMC_SDCFG1_RDLAT((int)((SDRAM_CASL*2) + 2))
            | MCF_SDRAMC_SDCFG1_ACT2RW((int)(((SDRAM_TRCD/SYSTEM_PERIOD) - 1) + 0.5))
            | MCF_SDRAMC_SDCFG1_PRE2ACT((int)(((SDRAM_TRP/SYSTEM_PERIOD) - 1) + 0.5))
            | MCF_SDRAMC_SDCFG1_REF2ACT((int)(((SDRAM_TRFC/SYSTEM_PERIOD) - 1) + 0.5))
            | MCF_SDRAMC_SDCFG1_WTLAT(3)
            );
        MCF_SDRAMC_SDCFG2 = (0
            | MCF_SDRAMC_SDCFG2_BRD2PRE(4)
            | MCF_SDRAMC_SDCFG2_BWT2RW(6)
            | MCF_SDRAMC_SDCFG2_BRD2WT(3)
            | MCF_SDRAMC_SDCFG2_BL(7)
            );

        /*
         * Precharge and enable write to SDMR
         */
        MCF_SDRAMC_SDCR = (0
            | MCF_SDRAMC_SDCR_MODE_EN
            | MCF_SDRAMC_SDCR_CKE
            | MCF_SDRAMC_SDCR_DDR
            | MCF_SDRAMC_SDCR_MUX(1)
            | MCF_SDRAMC_SDCR_RCNT((int)(((SDRAM_TREFI/(SYSTEM_PERIOD*64)) - 1) + 0.5))
            | MCF_SDRAMC_SDCR_IPALL
            );

#endif

        /*
         * Write extended mode register
         */
        MCF_SDRAMC_SDMR = (0
            | MCF_SDRAMC_SDMR_BNKAD_LEMR
            | MCF_SDRAMC_SDMR_AD(0x0)
            | MCF_SDRAMC_SDMR_CMD
            );

        /*
         * Write mode register and reset DLL
         */
        MCF_SDRAMC_SDMR = (0
            | MCF_SDRAMC_SDMR_BNKAD_LMR
            | MCF_SDRAMC_SDMR_AD(0x163)
            | MCF_SDRAMC_SDMR_CMD
            );

        /*
         * Execute a PALL command
         */
        MCF_SDRAMC_SDCR |= MCF_SDRAMC_SDCR_IPALL;

        /*
         * Perform two REF cycles
         */
        MCF_SDRAMC_SDCR |= MCF_SDRAMC_SDCR_IREF;
        MCF_SDRAMC_SDCR |= MCF_SDRAMC_SDCR_IREF;

        /*
         * Write mode register and clear reset DLL
         */
        MCF_SDRAMC_SDMR = (0
            | MCF_SDRAMC_SDMR_BNKAD_LMR
            | MCF_SDRAMC_SDMR_AD(0x063)
            | MCF_SDRAMC_SDMR_CMD
            );

        /*
         * Enable auto refresh and lock SDMR
         */
        MCF_SDRAMC_SDCR &= ~MCF_SDRAMC_SDCR_MODE_EN;
        MCF_SDRAMC_SDCR |= (0
            | MCF_SDRAMC_SDCR_REF
            | MCF_SDRAMC_SDCR_DQS_OE(0xF)
            );

//  }
}
/********************************************************************/
void
platform_led_display(int number)
{
}
/********************************************************************/
void
platform_handle_interrupt (int vector)
{
    switch (vector)
    {
        case 65: /* Eport Interrupt 1 */
        case 66: /* Eport Interrupt 2 */
        case 67: /* Eport Interrupt 3 */
        case 68: /* Eport Interrupt 4 */
        case 69: /* Eport Interrupt 5 */
        case 70: /* Eport Interrupt 6 */
        case 71: /* Eport Interrupt 7 */

            /* 
             * Clear the interrupt source 
             * This clears the flag for edge triggered interrupts
             */
            MCF_EPORT_EPFR = (uint8)(0x01 << (vector - 64));
            printf("External Interrupt #%d\n",vector - 64);
            break;  
    }
}
/********************************************************************/