jamaica.c

Freescale MCF5445evb 参考测试代码

/*!
 * \file    jamaica.c
 * \brief   Platform specific startup routines
 *
 * This file contains all platform specific routines necessary for
 * hardware startup and any platform dependent routines useful in
 * applications.
 *
 * \version $Revision: 1.8 $
 * \author  Michael Norman
 */

#include "common.h"
#include "uart.h"
#include "clock.h"

/********************************************************************/

static void platform_fbcs_init(void);
static void platform_sdramc_init(void);

/********************************************************************/
/*!
 * \brief   Jamaica startup routine
 * \return  None
 *
 * This is the top-level startup routine for Jamaica.  All the heavy
 * lifting is done in the modularized init routines.
 */
void
platform_startup (void)
{
    int pll_flags;
    UART_INFO uart_info;
    
    /*! \todo Determine input frequency */
    
    /* Initialize the on-chip system PLL */
    pll_flags = 0
    //    | CLOCK_PLL_LOLDIS
        | CLOCK_PLL_LOLIRQ;
        
    if (FREF == 33333333)
        pll_flags |= CLOCK_PLL_FBCLK_DIV8;
    
    clock_pll_init(FREF, FSYS, pll_flags, NULL);
    
    /* Initialize the default UART terminal port */
    uart_info.chan = TERM_PORT;
    uart_info.baud = TERM_BAUD;
    uart_info.dbits = UART_DATA_BITS_8;
    uart_info.sbits = UART_STOP_BITS_1;
    uart_info.parity = UART_PARTIY_NONE;
    uart_info.dma = FALSE;
    uart_info.ffull = FALSE;
    uart_info.flow = FALSE;
    uart_info.clkfreq = FBUS;
    uart_info.clksrc = NULL;
    uart_init((UART_INFO *)&uart_info);

    /* Initialize the Flexbus */
    platform_fbcs_init();

    /* Initialize the SDRAM controller */
    platform_sdramc_init();

#ifdef DEBUG_PRINT
    /* Determine board revision */
    printf("Jamaica (Rev X%d)\n", CPLD_VERSION+1);

    /* Determine boot mode */
    printf("Boot Mode: ");
    switch (CPLD_MODE & CPLD_MODE_BOOTMOD_MASK)
    {
        case CPLD_MODE_BOOTMOD_00:
            printf("00 - Defaults\n");
            break;
        case CPLD_MODE_BOOTMOD_01:
            printf("01 - Reserved\n");
            break;
        case CPLD_MODE_BOOTMOD_10:
            printf("10 - Parallel\n");
            break;
        case CPLD_MODE_BOOTMOD_11:
            printf("11 - Serial\n");
            break;
    }
#endif
}
/********************************************************************/
/*!
 * \brief   Initialize the Flexbus interface
 * \return  None
 *
 * Jamaica uses four chip-selects:
 *  - FBCS[0|1] : Flash 0 (U12, Atmel AT49BV040, 512KB)
 *  - FBCS[0|1] : Flash 1 (U903, Intel 28F128J3D, 16MB)
 *  - FBCS[2]   : Xilinx CPLD (U15, XC95144XL)
 *  - FBCS[3]   : Xilinx FPGA (U919, XC3S400)
 *
 * The CPLD maps FB_CS[1:0] to the two flash devcies based on the value
 * of the configuration switch CPLD_MODE[2] at reset.  This initialization
 * routine reads the CPLD settings to determine which flash is connected
 * to which chip-select.
 *
 * The Flexbus memory map is independent of the CPLD_MODE[2] setting
 * and is organized as follows:
 *\verbatim
 *
 *  Device   Port-size     Start     Size
 * ---------------------------------------
 *  Flash1      16      0x0000_0000   16M
 *  Flash0      8       0x0400_0000  512K
 *   CPLD       8       0x0800_0000   16M
 *   FPGA       32      0x0900_0000   16M
 *\endverbatim
 */
static void
platform_fbcs_init (void)
{
    int flash0_cs, flash1_cs, ws, sws, fb_period;

    /* Make sure the Flexbus signals are set for Flexbus functionality */
    MCF_GPIO_PAR_FBCTL = 0
        | MCF_GPIO_PAR_FBCTL_OE_OE
        | MCF_GPIO_PAR_FBCTL_TA_TA
        | MCF_GPIO_PAR_FBCTL_RW_RW
        | MCF_GPIO_PAR_FBCTL_TS_TS;
    MCF_GPIO_PAR_BE = 0
        | MCF_GPIO_PAR_BE_BE3_BE3
        | MCF_GPIO_PAR_BE_BE2_BE2
        | MCF_GPIO_PAR_BE_BE1_BE1
        | MCF_GPIO_PAR_BE_BE0_BE0;
        
    /* The global chip-select (FBCS0) will assert for all Flexbus
     * accesses until the CSMR0[V] bit is set.  CS0 must be enabled
     * before the CPLD config register can be read.  The reset values
     * are left untouched except for the address mask. Both flash devices
     * will be contained within the first 128M of Flexbus address, so
     * CS0 is given all 128M for now. */
    MCF_FBCS_CSMR0 = 0
        | MCF_FBCS_CSMR_BAM_128M
        | MCF_FBCS_CSMR_V;

    /* Enable CPLD chip-select */
    MCF_FBCS_CSAR2 = MCF_FBCS_CSAR_BA(CPLD_ADDRESS);
    MCF_FBCS_CSCR2 = 0
        | MCF_FBCS_CSCR_AA          /* Auto acknowledge */
        | MCF_FBCS_CSCR_WS(8)       /* Wait states */
        | MCF_FBCS_CSCR_PS_8        /* Port size: 8 bits */
        | MCF_FBCS_CSCR_RDAH(1)     /* Read address hold */
        | MCF_FBCS_CSCR_WRAH(1)     /* Write address hold */
        | MCF_FBCS_CSCR_ASET(1);     /* Address setup */
    MCF_FBCS_CSMR2 = 0
        | MCF_FBCS_CSMR_BAM((CPLD_SIZE-1)>>16)
        | MCF_FBCS_CSMR_V;          /* Activate this chip-select */

    /* Determine chip-select mapping */
    if (CPLD_MODE & CPLD_MODE_FLASH_CS) {
        flash1_cs = 0;
        flash0_cs = 1;
    }
    else {
        flash1_cs = 1;
        flash0_cs = 0;
    }
        
    /* Determine flash wait states. The maximum access time for the flashes
     * are defined in jamaica.h.  The chip-select is delayed ~7.5ns
     * through the CPLD.  The wait states are calculated assuming
     * that the entire access time is covered by wait-states.  This
     * allows the one clock of normal access time (pre wait-states)
     * to cover the additional delay through the CPLD.
     */
    ws = 1 + ((clock_get_ffb() / 1000000) * FLASH0_MAX_ACCESS) / 1000;

    /* Enable Flash 0 (Atmel AT49BV040) chip-select */
    MCF_FBCS_CSAR(flash0_cs) = MCF_FBCS_CSAR_BA(FLASH0_ADDRESS);
    MCF_FBCS_CSCR(flash0_cs) = 0
        | MCF_FBCS_CSCR_AA          /* Auto acknowledge */
        | MCF_FBCS_CSCR_WS(ws)      /* Wait states */
        | MCF_FBCS_CSCR_PS_8;       /* Port size: 8 bits */
    MCF_FBCS_CSMR(flash0_cs) = 0
        | MCF_FBCS_CSMR_BAM((FLASH0_SIZE-1)>>16)
        | MCF_FBCS_CSMR_V;          /* Activate this chip-select */

    /* Enable Flash 1 (Intel J3D) chip-select
     *
     * The interface to Flash 1 is a non-multiplexed 8-bit data bus / 24 bit
     * address bus interface.
     * 
     * The J3D flash defaults to asynchronous page-mode which allows
     * burst reads. Secondary wait-states can be used to realize this timing 
     * (otherwise, the Flexbus will use the normal wait-states for all burst
     * beats). The SWS is calculated to allow for the output valid plus our
     * data setup time requirement of 3ns. 
     */
    ws = 1 + ((clock_get_ffb() / 1000000) * FLASH1_MAX_ACCESS) / 1000;
    //sws = (FLASH1_PAGE_MAX_ACCESS + 3) / fb_period;
    MCF_FBCS_CSAR(flash1_cs) = MCF_FBCS_CSAR_BA(FLASH1_ADDRESS);
    MCF_FBCS_CSCR(flash1_cs) = 0
    //    | MCF_FBCS_CSCR_BSTR        /* Burst Reads (asynch page-mode reads) */
        | MCF_FBCS_CSCR_AA          /* Auto acknowledge */
        | MCF_FBCS_CSCR_WS(ws)      /* Wait states */
        | MCF_FBCS_CSCR_RDAH(0)     /* Read address hold */
        | MCF_FBCS_CSCR_WRAH(0)     /* Write address hold */
        | MCF_FBCS_CSCR_ASET(0)     /* Address setup */
    //    | MCF_FBCS_CSCR_SWSEN       /* Secondary wait-states enable */
    //    | MCF_FBCS_CSCR_SWS(sws)    /* Secondary wait-states */
        | MCF_FBCS_CSCR_PS_8;       /* Port size: 8 bits */
    MCF_FBCS_CSMR(flash1_cs) = 0
        | MCF_FBCS_CSMR_BAM((FLASH1_SIZE-1)>>16)
        | MCF_FBCS_CSMR_V;          /* Activate this chip-select */

    /* Enable FPGA chip-select */
    MCF_FBCS_CSAR3 = MCF_FBCS_CSAR_BA(FPGA_ADDRESS);
    MCF_FBCS_CSCR3 = 0
        | MCF_FBCS_CSCR_AA          /* Auto acknowledge */
        | MCF_FBCS_CSCR_WS(8)       /* Wait states */
        | MCF_FBCS_CSCR_PS_32;      /* Port size: 32 bits */
    MCF_FBCS_CSMR3 = 0
        | MCF_FBCS_CSMR_BAM((FPGA_SIZE-1)>>16)
        | MCF_FBCS_CSMR_V;          /* Activate this chip-select */
}
/********************************************************************/
/*!
 * \brief   Initialize the SDRAM Controller
 * \return  None
 *
 * There are four MT47H64M8 (512Mb, 16Meg x 8 x 4 banks) DDR2 chips
 * on Jamamica; two on each of the two chip-selects.  This provides
 * a total of 256MB of DDR2 memory.
 *
 * SDRAM timing and configuration notes:
 *  - Burst Length: On this architecture, the internal bus is 32-bits and the
 *    SDRAM data bus is 16-bits.  Thus a 4 beat burst on the internal bus will
 *    result in an 8 beat burst to the SDRAM
 *  - CAS Latency: The bus is only running at a max of 133/266MHz; in the low
 *    end of DDR2 capabilites.  The lowest CAS latency setting of 3 will work
 *    for all DDR2 devices.
 *  - Additive Latency: Typical additive latency setting would be
 *    tRCD(min)-1 tCLKs.  At 133/266MHz, this usually works out to be
 *    one clock of AL.
 *  - Address Mux: The MT47H64M8 is organized as 64M x 8bit with 14 row
 *    addresses, 10 column addresses, and 4 banks (14 x 10 x 4).  This
 *    calls for an address mux setting (SDCR[ADDR_MUX]) of 2 as shown in
 *    Tables 20-2,3 in the MCF54455RM.
 */
static void
platform_sdramc_init (void)
{
    /* Only execute this init if the controller isn't already enabled */
    if (!(MCF_SDRAMC_SDCR & MCF_SDRAMC_SDCR_REF_EN))
    {
        /* Program the SDRAMC pins to DDR2 mode */
        MCF_GPIO_MSCR_SDRAM = 0
            | MCF_GPIO_MSCR_SDRAM_SDDATA_DDR2
            | MCF_GPIO_MSCR_SDRAM_SDDQS_DDR2
            | MCF_GPIO_MSCR_SDRAM_SDCLK_DDR2
            | MCF_GPIO_MSCR_SDRAM_SDCTL_DDR2;

        /* Initialize SDRAM chip selects */
        MCF_SDRAMC_SDCS0 = 0
            | MCF_SDRAMC_SDCS_BA(SDRAM_ADDRESS)
            | MCF_SDRAMC_SDCS_CSSZ_128MBYTE;
        MCF_SDRAMC_SDCS1 = 0
            | MCF_SDRAMC_SDCS_BA(SDRAM_ADDRESS + (128 * 1024 * 1024))
            | MCF_SDRAMC_SDCS_CSSZ_128MBYTE;

        /* Configuration Register 1 */
        MCF_SDRAMC_SDCFG1 = 0
            | MCF_SDRAMC_SDCFG1_SRD2RWP(8/2+2)
            | MCF_SDRAMC_SDCFG1_SWT2RWP(SDRAM_SWT2RWP)
            | MCF_SDRAMC_SDCFG1_RD_LAT(SDRAM_CL)
            | MCF_SDRAMC_SDCFG1_ACT2RW(SDRAM_ACT2RW)
            | MCF_SDRAMC_SDCFG1_PRE2ACT(SDRAM_PRE2ACT)
            | MCF_SDRAMC_SDCFG1_REF2ACT(SDRAM_REF2ACT)
            | MCF_SDRAMC_SDCFG1_WT_LAT(SDRAM_AL);

        /* Configuration Register 2 */
        MCF_SDRAMC_SDCFG2 = 0
            | MCF_SDRAMC_SDCFG2_BRD2RP(8/2+SDRAM_AL)
            | MCF_SDRAMC_SDCFG2_BWT2RWP(SDRAM_BWT2RWP)
            | MCF_SDRAMC_SDCFG2_BRD2W(8/2+2)
            | MCF_SDRAMC_SDCFG2_BL(8-1);

        /* Precharge and enable write to SDMR */
        MCF_SDRAMC_SDCR = 0
            | MCF_SDRAMC_SDCR_MODE_EN
            | MCF_SDRAMC_SDCR_CKE
            | MCF_SDRAMC_SDCR_DDR_MODE
            | MCF_SDRAMC_SDCR_DDR2_MODE
            | MCF_SDRAMC_SDCR_ADDR_MUX(2)
            | MCF_SDRAMC_SDCR_REF_CNT(SDRAM_REFCNT)
            | MCF_SDRAMC_SDCR_MEM_PS
            | MCF_SDRAMC_SDCR_IPALL;

        /* Write extended mode register */
        MCF_SDRAMC_SDMR = 0
            | MCF_SDRAMC_SDMR_BK_LEMR
            | MCF_SDRAMC_SDMR_DDR2_AD(0
                | 1 << 10
                | SDRAM_AL << 3)
            | MCF_SDRAMC_SDMR_CMD;

        /* Write mode register and reset DLL */
        MCF_SDRAMC_SDMR = 0
            | MCF_SDRAMC_SDMR_BK_LMR
            | MCF_SDRAMC_SDMR_DDR2_AD(0
                | SDRAM_WR << 9
                | 1 << 8
                | 3 << 4
                | 3 << 0)
            | MCF_SDRAMC_SDMR_CMD;

        /* Execute a PALL command */
        MCF_SDRAMC_SDCR |= MCF_SDRAMC_SDCR_IPALL;

        /* Perform two REF cycles */
        MCF_SDRAMC_SDCR |= MCF_SDRAMC_SDCR_IREF;
        MCF_SDRAMC_SDCR |= MCF_SDRAMC_SDCR_IREF;

        /* Write mode register and clear reset DLL */
        MCF_SDRAMC_SDMR = 0
            | MCF_SDRAMC_SDMR_BK_LMR
            | MCF_SDRAMC_SDMR_DDR2_AD(0
                | SDRAM_WR << 9
                | 3 << 4
                | 3 << 0)
            | MCF_SDRAMC_SDMR_CMD;

        /* Enable auto refresh and lock SDMR */
        MCF_SDRAMC_SDCR &= ~MCF_SDRAMC_SDCR_MODE_EN;
        MCF_SDRAMC_SDCR |= 0
            | MCF_SDRAMC_SDCR_REF_EN
            | MCF_SDRAMC_SDCR_DQS_OE_BOTH;
    }
}
/********************************************************************/
/*!
 * \brief   Write to the 7-segment display via the FPGA
 * \param   number  The two digit number to be written to the display
 * \return  None
 *
 * The FPGA controls a 7-segment display.  The value written into the TBD
 * register will be converted by the FPGA so that it appears on the
 * display.
 *
 * \todo    platform_led_display()
 */
void
platform_led_display(int number)
{
    FPGA_7SEGMENT = number;
    //CPLD_LEDS = number;
}
/********************************************************************/
/*!
 * \brief   Handle platform specific interrupt
 * \param   vector  Interrupt vector number to handle
 * \return  None
 *
 * This routine handles all user defined vectors that don't have
 * a specific handler registered in the vector table.
 */
void
platform_handle_interrupt (int vector)
{
    switch (vector)
    {
        case 65: /* Eport Interrupt 1 */
        case 66: /* Eport Interrupt 2 */
        case 67: /* Eport Interrupt 3 */
        case 68: /* Eport Interrupt 4 */
        case 69: /* Eport Interrupt 5 */
        case 70: /* Eport Interrupt 6 */
        case 71: /* Eport Interrupt 7 */

            /*
             * Clear the interrupt source
             * This clears the flag for edge triggered interrupts
             */
            MCF_EPORT_EPFR = (uint8)(0x01 << (vector - 64));
            printf("External Interrupt #%d\n",vector - 64);
            break;
    }
}
/********************************************************************/
/*!
 * \brief   Enable all the external interrupts on the platform
 * \return  None
 *
 * Enable the extneral interrupts in the MCF5445x and enabled the two
 * switches for interrupt generation in the M54455EVB FPGA.
 *
 * \note    The generic interrupt handler will be called unless the 
 *          application registers a custom one.  Example:
 *          mcf5xxx_set_handler(64 + 4, (ADDRESS)sw6_handler);
 */
void
platform_enable_interrupts (void)
{
    /* Enable interrupts in the Edge Port */
    MCF_EPORT_EPPAR = 0
        | MCF_EPORT_EPPAR_EPPA1_RISING
        | MCF_EPORT_EPPAR_EPPA3_RISING
        | MCF_EPORT_EPPAR_EPPA4_RISING
        | MCF_EPORT_EPPAR_EPPA7_LEVEL;
    MCF_EPORT_EPIER = 0
        | MCF_EPORT_EPIER_EPIE1
        | MCF_EPORT_EPIER_EPIE3
        | MCF_EPORT_EPIER_EPIE4
        | MCF_EPORT_EPIER_EPIE7;

    /* Enable interrupts in the interrupt controller */
    MCF_INTC0_CIMR = MCF_INTC0_ICR1 = 1;
    MCF_INTC0_CIMR = MCF_INTC0_ICR3 = 3;
    MCF_INTC0_CIMR = MCF_INTC0_ICR4 = 4;
    MCF_INTC0_CIMR = MCF_INTC0_ICR7 = 7;
    
    /* Enable interrupts in the FPGA */
    FPGA_IRQEN = 0
        | FPGA_IRQEN_SW7
        | FPGA_IRQEN_SW6;
        
    /* Route the switch interrupts to IRQ7 & IRQ4 */
    FPGA_IRQROUTE = 0
        | FPGA_IRQROUTE_SW7_IRQ7
        | FPGA_IRQROUTE_SW6_IRQ4;
    
    /* Enable interrupts in the core */
    mcf5xxx_irq_enable();
}
/********************************************************************/
void 
platform_gpio_config(int setting)
{

}
/********************************************************************/