m54451evb.c

Freescale MCF5445evb 参考测试代码

/*!
 * \file    m54451evb.c
 * \brief   Platform specific startup routines
 *
 * This file contains all platform specific routines necessary for
 * hardware startup and any platform dependent routines useful in
 * applications.
 *
 * \version $Revision: 1.1 $
 * \author  Michael Norman
 */

#include "common.h"
#include "uart.h"
#include "clock.h"

/********************************************************************/

static void platform_fbcs_init(void);
static void platform_sdramc_init(void);

/********************************************************************/
/*!
 * \brief   Jamaica startup routine
 * \return  None
 *
 * This is the top-level startup routine for Jamaica.  All the heavy
 * lifting is done in the modularized init routines.
 */
void
platform_startup (void)
{
    int pll_flags;
    UART_INFO uart_info;
    
    /* Initialize the on-chip system PLL */
    pll_flags = 0
    //    | CLOCK_PLL_LOLDIS
        | CLOCK_PLL_LOLIRQ;
        
    clock_pll_init(FREF, FSYS, pll_flags, NULL);
    
    /* Initialize the default UART terminal port */
    uart_info.chan = TERM_PORT;
    uart_info.baud = TERM_BAUD;
    uart_info.dbits = UART_DATA_BITS_8;
    uart_info.sbits = UART_STOP_BITS_1;
    uart_info.parity = UART_PARTIY_NONE;
    uart_info.dma = FALSE;
    uart_info.ffull = FALSE;
    uart_info.flow = FALSE;
    uart_info.clkfreq = FBUS;
    uart_info.clksrc = NULL;
    uart_init((UART_INFO *)&uart_info);

    /* Initialize the Flexbus */
    platform_fbcs_init();

    /* Initialize the SDRAM controller */
    //platform_sdramc_init();
}
/********************************************************************/
/*!
 * \brief   Initialize the Flexbus interface
 * \return  None
 */
static void
platform_fbcs_init (void)
{
    int flash0_cs, flash1_cs, ws, sws, fb_period;

    /* Make sure the Flexbus signals are set for Flexbus functionality */
    MCF_GPIO_PAR_FBCTL = 0
        | MCF_GPIO_PAR_FBCTL_OE_OE
        | MCF_GPIO_PAR_FBCTL_TA_TA
        | MCF_GPIO_PAR_FBCTL_RW_RW
        | MCF_GPIO_PAR_FBCTL_TS_TS;
    MCF_GPIO_PAR_BE = 0
        | MCF_GPIO_PAR_BE_BE3_BE3
        | MCF_GPIO_PAR_BE_BE2_BE2
        | MCF_GPIO_PAR_BE_BE1_BE1
        | MCF_GPIO_PAR_BE_BE0_BE0;
        
    /* Determine flash wait states. The maximum access time for the flashes
     * are defined in jamaica.h.  The chip-select is delayed ~7.5ns
     * through the CPLD.  The wait states are calculated assuming
     * that the entire access time is covered by wait-states.  This
     * allows the one clock of normal access time (pre wait-states)
     * to cover the additional delay through the CPLD.
     */
    ws = 1 + ((clock_get_ffb() / 1000000) * FLASH_MAX_ACCESS) / 1000;

    /* Enable Flash 0 (Atmel AT49BV040) chip-select */
    MCF_FBCS_CSAR(0) = MCF_FBCS_CSAR_BA(FLASH_ADDRESS);
    MCF_FBCS_CSCR(0) = 0
        | MCF_FBCS_CSCR_AA          /* Auto acknowledge */
        | MCF_FBCS_CSCR_WS(ws)      /* Wait states */
        | MCF_FBCS_CSCR_PS_8;       /* Port size: 8 bits */
    MCF_FBCS_CSMR(0) = 0
        | MCF_FBCS_CSMR_BAM((FLASH_SIZE-1)>>16)
        | MCF_FBCS_CSMR_V;          /* Activate this chip-select */

}
/********************************************************************/
/*!
 * \brief   Initialize the SDRAM Controller
 * \return  None
 *
 * There are four MT47H64M8 (512Mb, 16Meg x 8 x 4 banks) DDR2 chips
 * on Jamamica; two on each of the two chip-selects.  This provides
 * a total of 256MB of DDR2 memory.
 *
 * SDRAM timing and configuration notes:
 *  - Burst Length: On this architecture, the internal bus is 32-bits and the
 *    SDRAM data bus is 16-bits.  Thus a 4 beat burst on the internal bus will
 *    result in an 8 beat burst to the SDRAM
 *  - CAS Latency: The bus is only running at a max of 133/266MHz; in the low
 *    end of DDR2 capabilites.  The lowest CAS latency setting of 3 will work
 *    for all DDR2 devices.
 *  - Additive Latency: Typical additive latency setting would be
 *    tRCD(min)-1 tCLKs.  At 133/266MHz, this usually works out to be
 *    one clock of AL.
 *  - Address Mux: The MT47H64M8 is organized as 64M x 8bit with 14 row
 *    addresses, 10 column addresses, and 4 banks (14 x 10 x 4).  This
 *    calls for an address mux setting (SDCR[ADDR_MUX]) of 2 as shown in
 *    Tables 20-2,3 in the MCF54455RM.
 */
static void
platform_sdramc_init (void)
{
    /* Only execute this init if the controller isn't already enabled */
    if (!(MCF_SDRAMC_SDCR & MCF_SDRAMC_SDCR_REF_EN))
    {
        /* Program the SDRAMC pins to DDR2 mode */
        MCF_GPIO_MSCR_SDRAM = 0
            | MCF_GPIO_MSCR_SDRAM_SDDATA_DDR2
            | MCF_GPIO_MSCR_SDRAM_SDDQS_DDR2
            | MCF_GPIO_MSCR_SDRAM_SDCLK_DDR2
            | MCF_GPIO_MSCR_SDRAM_SDCTL_DDR2;

        /* Initialize SDRAM chip selects */
        MCF_SDRAMC_SDCS0 = 0
            | MCF_SDRAMC_SDCS_BA(SDRAM_ADDRESS)
            | MCF_SDRAMC_SDCS_CSSZ_128MBYTE;
        MCF_SDRAMC_SDCS1 = 0
            | MCF_SDRAMC_SDCS_BA(SDRAM_ADDRESS + (128 * 1024 * 1024))
            | MCF_SDRAMC_SDCS_CSSZ_128MBYTE;

        /* Configuration Register 1 */
        MCF_SDRAMC_SDCFG1 = 0
            | MCF_SDRAMC_SDCFG1_SRD2RWP(8/2+2)
            | MCF_SDRAMC_SDCFG1_SWT2RWP(SDRAM_SWT2RWP)
            | MCF_SDRAMC_SDCFG1_RD_LAT(SDRAM_CL)
            | MCF_SDRAMC_SDCFG1_ACT2RW(SDRAM_ACT2RW)
            | MCF_SDRAMC_SDCFG1_PRE2ACT(SDRAM_PRE2ACT)
            | MCF_SDRAMC_SDCFG1_REF2ACT(SDRAM_REF2ACT)
            | MCF_SDRAMC_SDCFG1_WT_LAT(SDRAM_AL);

        /* Configuration Register 2 */
        MCF_SDRAMC_SDCFG2 = 0
            | MCF_SDRAMC_SDCFG2_BRD2RP(8/2+SDRAM_AL)
            | MCF_SDRAMC_SDCFG2_BWT2RWP(SDRAM_BWT2RWP)
            | MCF_SDRAMC_SDCFG2_BRD2W(8/2+2)
            | MCF_SDRAMC_SDCFG2_BL(8-1);

        /* Precharge and enable write to SDMR */
        MCF_SDRAMC_SDCR = 0
            | MCF_SDRAMC_SDCR_MODE_EN
            | MCF_SDRAMC_SDCR_CKE
            | MCF_SDRAMC_SDCR_DDR_MODE
            | MCF_SDRAMC_SDCR_DDR2_MODE
            | MCF_SDRAMC_SDCR_ADDR_MUX(2)
            | MCF_SDRAMC_SDCR_REF_CNT(SDRAM_REFCNT)
            | MCF_SDRAMC_SDCR_MEM_PS
            | MCF_SDRAMC_SDCR_IPALL;

        /* Write extended mode register */
        MCF_SDRAMC_SDMR = 0
            | MCF_SDRAMC_SDMR_BK_LEMR
            | MCF_SDRAMC_SDMR_DDR2_AD(0
                | 1 << 10
                | SDRAM_AL << 3)
            | MCF_SDRAMC_SDMR_CMD;

        /* Write mode register and reset DLL */
        MCF_SDRAMC_SDMR = 0
            | MCF_SDRAMC_SDMR_BK_LMR
            | MCF_SDRAMC_SDMR_DDR2_AD(0
                | SDRAM_WR << 9
                | 1 << 8
                | 3 << 4
                | 3 << 0)
            | MCF_SDRAMC_SDMR_CMD;

        /* Execute a PALL command */
        MCF_SDRAMC_SDCR |= MCF_SDRAMC_SDCR_IPALL;

        /* Perform two REF cycles */
        MCF_SDRAMC_SDCR |= MCF_SDRAMC_SDCR_IREF;
        MCF_SDRAMC_SDCR |= MCF_SDRAMC_SDCR_IREF;

        /* Write mode register and clear reset DLL */
        MCF_SDRAMC_SDMR = 0
            | MCF_SDRAMC_SDMR_BK_LMR
            | MCF_SDRAMC_SDMR_DDR2_AD(0
                | SDRAM_WR << 9
                | 3 << 4
                | 3 << 0)
            | MCF_SDRAMC_SDMR_CMD;

        /* Enable auto refresh and lock SDMR */
        MCF_SDRAMC_SDCR &= ~MCF_SDRAMC_SDCR_MODE_EN;
        MCF_SDRAMC_SDCR |= 0
            | MCF_SDRAMC_SDCR_REF_EN
            | MCF_SDRAMC_SDCR_DQS_OE_BOTH;
    }
}
/********************************************************************/
/*!
 * \brief   Write to the LEDs
 * \param   number  The single digit number to be displayed
 * \return  None
 */
void
platform_led_display(int number)
{
//TBD
}
/********************************************************************/
/*!
 * \brief   Handle platform specific interrupt
 * \param   vector  Interrupt vector number to handle
 * \return  None
 *
 * This routine handles all user defined vectors that don't have
 * a specific handler registered in the vector table.
 */
void
platform_handle_interrupt (int vector)
{
    switch (vector)
    {
        case 65: /* Eport Interrupt 1 */
        case 66: /* Eport Interrupt 2 */
        case 67: /* Eport Interrupt 3 */
        case 68: /* Eport Interrupt 4 */
        case 69: /* Eport Interrupt 5 */
        case 70: /* Eport Interrupt 6 */
        case 71: /* Eport Interrupt 7 */

            /*
             * Clear the interrupt source
             * This clears the flag for edge triggered interrupts
             */
            MCF_EPORT_EPFR = (uint8)(0x01 << (vector - 64));
            printf("External Interrupt #%d\n",vector - 64);
            break;
    }
}
/********************************************************************/
/*!
 * \brief   Enable all the external interrupts on the platform
 * \return  None
 *
 * Enable the extneral interrupts in the MCF5445x.
 *
 * \note    The generic interrupt handler will be called unless the 
 *          application registers a custom one.  Example:
 *          mcf5xxx_set_handler(64 + 4, (ADDRESS)irq4_handler);
 */
void
platform_enable_interrupts (void)
{
    /* Enable interrupts in the Edge Port */
    MCF_EPORT_EPPAR = 0
        | MCF_EPORT_EPPAR_EPPA1_RISING
        | MCF_EPORT_EPPAR_EPPA3_RISING
        | MCF_EPORT_EPPAR_EPPA4_RISING
        | MCF_EPORT_EPPAR_EPPA7_LEVEL;
    MCF_EPORT_EPIER = 0
        | MCF_EPORT_EPIER_EPIE1
        | MCF_EPORT_EPIER_EPIE3
        | MCF_EPORT_EPIER_EPIE4
        | MCF_EPORT_EPIER_EPIE7;

    /* Enable interrupts in the interrupt controller */
    MCF_INTC0_CIMR = MCF_INTC0_ICR1 = 1;
    MCF_INTC0_CIMR = MCF_INTC0_ICR3 = 3;
    MCF_INTC0_CIMR = MCF_INTC0_ICR4 = 4;
    MCF_INTC0_CIMR = MCF_INTC0_ICR7 = 7;
    
    /* Enable interrupts in the core */
    mcf5xxx_irq_enable();
}
/********************************************************************/
void 
platform_gpio_config(int setting)
{
//TBD
}
/********************************************************************/