📄 m54451evb.h
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/*! * \file m54451evb.h * \brief Platform specific C defines * * This file contains all platform specific routines necessary for * hardware startup and useful platform dependent routines. * * \author Michael Norman * \version $Revision: 1.1 $ */#ifndef __M54451EVB_H__#define __M54451EVB_H__/********************************************************************//* * System Clock Settings */#ifndef FREF#define FREF 24000000#endif#ifndef FSYS#define FSYS 240000000 /*!< Core clock freq (Hz) */#endif#define FSYS_KHZ (FSYS/1000) /*!< Core clock freq (KHz) */#define FSYS_MHZ (FSYS_KHZ/1000) /*!< Core clock freq (MHz) */#define TSYS_NS (1000/FSYS_MHZ) /*!< Core clock period (ns) */#define FBUS (FSYS/2) /*!< Internal bus clock freq (Hz) */#define FBUS_KHZ (FSYS_KHZ/2) /*!< Internal bus clock freq (KHz) */#define FBUS_MHZ (FSYS_MHZ/2) /*!< Internal bus clock freq (MHz) */#define TBUS_NS (1000/FBUS_MHZ) /*!< Internal bus clock period (ns) *//* * Serial Port Info */#define TERM_PORT 0 /*!< UART channel used as terminal */#define TERM_BAUD 115200 /*!< Default UART baud rate *//* * Flash Info *///TBD#define ATMEL_FLASH_AT49BV040A /*!< Flash device */#define FLASH_MAX_ACCESS 90 /*!< Flash maximum access time *//* * SDRAM Timing Parameters from DDR2 Specs */#define SDRAM_CL 3 /*!< DDR2 CAS Latency */#define SDRAM_AL 1 /*!< DDR2 Additive Latency */#define SDRAM_TRCD (15/TBUS_NS) /*!< DDR2 RAS to CAS delay (ns) */#define SDRAM_TRP (15/TBUS_NS) /*!< DDR2 Precharge commadn period (ns) */#define SDRAM_TWR (15/TBUS_NS) /*!< DDR2 Write recovery time */#define SDRAM_TRFC 105 /*!< DDR2 Refresh to Active interval (ns) */#define SDRAM_TREFI 7800 /*!< DDR2 Average refresh interval (ns) *//* * SDRAM timing calculations */#if (FSYS_KHZ == 240000)#define SDRAM_SWT2RWP 5 /* SDRAM_CL + SDRAM_AL + SDRAM_TWR */#define SDRAM_ACT2RW 1 /* SDRAM_TRCD */#define SDRAM_PRE2ACT 1 /* SDRAM_TRP */#define SDRAM_REF2ACT 8 /* SDRAM_TRFC/(TBUS_NS * 2) + 1 */#define SDRAM_BWT2RWP 9 /* SDRAM_CL + SDRAM_AL + 8/2 + SDRAM_TWR */#define SDRAM_REFCNT 15 /* SDRAM_TREFI/(TBUS_NS*64) - 1 */#define SDRAM_WR 1 /* SDRAM_TWR */#elif (FSYS_KHZ == 200000)#define SDRAM_SWT2RWP 5 /* SDRAM_CL + SDRAM_AL + SDRAM_TWR */#define SDRAM_ACT2RW 1 /* SDRAM_TRCD */#define SDRAM_PRE2ACT 1 /* SDRAM_TRP */#define SDRAM_REF2ACT 6 /* SDRAM_TRFC/(TBUS_NS * 2) + 1 */#define SDRAM_BWT2RWP 9 /* SDRAM_CL + SDRAM_AL + 8/2 + SDRAM_TWR */#define SDRAM_REFCNT 11 /* SDRAM_TREFI/(TBUS_NS*64) - 1 */#define SDRAM_WR 1 /* SDRAM_TWR */#elif (FSYS_KHZ == 160000)#define SDRAM_SWT2RWP 5 /* SDRAM_CL + SDRAM_AL + SDRAM_TWR */#define SDRAM_ACT2RW 1 /* SDRAM_TRCD */#define SDRAM_PRE2ACT 1 /* SDRAM_TRP */#define SDRAM_REF2ACT 5 /* SDRAM_TRFC/(TBUS_NS * 2) + 1 */#define SDRAM_BWT2RWP 9 /* SDRAM_CL + SDRAM_AL + 8/2 + SDRAM_TWR */#define SDRAM_REFCNT 10 /* SDRAM_TREFI/(TBUS_NS*64) - 1 */#define SDRAM_WR 1 /* SDRAM_TWR */#else#error "What should I do?"#endif/* * Memory map definitions from linker command files */extern uint8 __FLASH[];extern uint8 __FLASH_SIZE[];extern uint8 __SDRAM[];extern uint8 __SDRAM_SIZE[];extern uint8 __SRAM[];extern uint8 __SRAM_SIZE[];/* * Memory Map Info */#define FLASH_ADDRESS (uint32)__FLASH #define FLASH_SIZE (uint32)__FLASH_SIZE#define SDRAM_ADDRESS (uint32)__SDRAM#define SDRAM_SIZE (uint32)__SDRAM_SIZE#define SRAM_ADDRESS (uint32)__SRAM#define SRAM_SIZE (uint32)__SRAM_SIZE/* * Board specific function prototypes */void platform_startup (void);void platform_handle_interrupt (int);void platform_enable_interrupts (void);void platform_led_display (int);void platform_gpio_config(int);/********************************************************************/#endif /* __M54451EVB_H__ */
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