📄 mem_map.h
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#define PIT_TRIG4 (140) #define PIT_TRIG5 (141) #define PIT_TRIG6 (142) #define PIT_TRIG7 (143) #define WDT_TRIG0 (144) #define WDT_TRIG1 (145) #define WDT_TRIG2 (146) #define WDT_TRIG3 (147) #define WDT_TRIG4 (148) #define WDT_TRIG5 (149) #define WDT_TRIG6 (150) #define WDT_TRIG7 (151) #define DMA_TRIG0 (152) #define DMA_TRIG1 (153) #define DMA_TRIG2 (154) #define DMA_TRIG3 (155) #define DMA_TRIG4 (156) #define DMA_TRIG5 (157) #define DMA_TRIG6 (158) #define DMA_TRIG7 (159) #define LCDC_TRIG0 (160) #define LCDC_TRIG1 (161) #define LCDC_TRIG2 (162) #define LCDC_TRIG3 (163) #define LCDC_TRIG4 (164) #define LCDC_TRIG5 (165) #define LCDC_TRIG6 (166) #define LCDC_TRIG7 (167) #define SDRAMC_TRIG0 (168) #define SDRAMC_TRIG1 (169) #define SDRAMC_TRIG2 (170) #define SDRAMC_TRIG3 (171) #define SDRAMC_TRIG4 (172) #define SDRAMC_TRIG5 (173) #define SDRAMC_TRIG6 (174) #define SDRAMC_TRIG7 (175) #define RTC_TRIG0 (176) #define RTC_TRIG1 (177) #define RTC_TRIG2 (178) #define RTC_TRIG3 (179) #define RTC_TRIG4 (180) #define RTC_TRIG5 (181) #define RTC_TRIG6 (182) #define RTC_TRIG7 (183) #define USB_TRIG0 (184) #define USB_TRIG1 (185) #define USB_TRIG2 (186) #define USB_TRIG3 (187) #define USB_TRIG4 (188) #define USB_TRIG5 (189) #define USB_TRIG6 (190) #define USB_TRIG7 (191) #define OPT_TRIG0 (192) #define OPT_TRIG1 (193) #define OPT_TRIG2 (194) #define OPT_TRIG3 (195) #define OPT_TRIG4 (196) #define OPT_TRIG5 (197) #define OPT_TRIG6 (198) #define OPT_TRIG7 (199) #define FEC_TRIG0 (200) #define FEC_TRIG1 (201) #define FEC_TRIG2 (202) #define FEC_TRIG3 (203) #define FEC_TRIG4 (204) #define FEC_TRIG5 (205) #define FEC_TRIG6 (206) #define FEC_TRIG7 (207) #define FEC_TRIG8 (208) #define FEC_TRIG9 (209) #define FEC_TRIG10 (210) #define FEC_TRIG11 (211) #define FEC_TRIG12 (212) #define FEC_TRIG13 (213) #define FEC_TRIG14 (214) #define FEC_TRIG15 (215) #define FEC_TRIG16 (216) #define GPIO_TRIG8 (217) #define GPIO_TRIG9 (218) #define GPIO_TRIG10 (219) #define GPIO_TRIG11 (220) #define PLL_TRIG0 (221) #define PLL_TRIG1 (222) #define PLL_TRIG2 (223) #define PLL_TRIG3 (224) #define PLL_TRIG4 (225) #define PLL_TRIG5 (226) #define TEA_TRIG0 (227) #define TEA_TRIG8 (228) #define FEC_TRIG17 (229) #define FEC_TRIG18 (230) #define FEC_TRIG19 (231) #define FEC_TRIG20 (232) /* define x_TRIGx 218 */ /* define x_TRIGx 219 */ /* define x_TRIGx 220 */ /* define x_TRIGx 221 */ /* define x_TRIGx 222 */ /* define x_TRIGx 223 */ /* define x_TRIGx 224 */ /* define x_TRIGx 225 */ /* define x_TRIGx 226 */ /* define x_TRIGx 227 */ /* define x_TRIGx 228 */ /* define x_TRIGx 229 */ /* define x_TRIGx 230 */ /* define x_TRIGx 231 */ /* define x_TRIGx 232 */ /* define x_TRIGx 233 */ /* define x_TRIGx 234 */ /* define x_TRIGx 235 */ /* define x_TRIGx 236 */ /* define x_TRIGx 237 */ /* define x_TRIGx 238 */ /* define x_TRIGx 239 */ /* define x_TRIGx 240 */ /* define x_TRIGx 241 */ /* define x_TRIGx 242 */ /* define x_TRIGx 243 */ /* define x_TRIGx 244 */ /* define x_TRIGx 245 */ /* define x_TRIGx 246 */ /* define x_TRIGx 247 */ /* define x_TRIGx 248 */ /* define x_TRIGx 249 */ /* define x_TRIGx 250 */ /* define x_TRIGx 251 */ /* define x_TRIGx 252 */ /* define x_TRIGx 253 */ /* define x_TRIGx 254 */ /* define x_TRIGx 255 */ /* ----------------------------------------------------------------------------- */ /* FEC */ /* ----------------------------------------------------------------------------- */ #define FEC0_IR (FEC_REG_BASE + 0x00000004) #define FEC0_IMR (FEC_REG_BASE + 0x00000008) #define FEC0_RDAR (FEC_REG_BASE + 0x00000010) #define FEC0_TDAR (FEC_REG_BASE + 0x00000014) #define FEC0_ECR (FEC_REG_BASE + 0x00000024) #define FEC0_MMFR (FEC_REG_BASE + 0x00000040) #define FEC0_MSCR (FEC_REG_BASE + 0x00000044) #define FEC0_MIBCR (FEC_REG_BASE + 0x00000064) #define FEC0_RCR (FEC_REG_BASE + 0x00000084) #define FEC0_TCR (FEC_REG_BASE + 0x000000C4) #define FEC0_PALR (FEC_REG_BASE + 0x000000E4) #define FEC0_PAHR (FEC_REG_BASE + 0x000000E8) #define FEC0_OPDR (FEC_REG_BASE + 0x000000EC) #define FEC0_IHTUR (FEC_REG_BASE + 0x00000118) #define FEC0_IHTLR (FEC_REG_BASE + 0x0000011C) #define FEC0_GHTUR (FEC_REG_BASE + 0x00000120) #define FEC0_GHTLR (FEC_REG_BASE + 0x00000124) #define FEC0_TFWR (FEC_REG_BASE + 0x00000144) #define FEC0_FRBR (FEC_REG_BASE + 0x0000014C) #define FEC0_FRSAR (FEC_REG_BASE + 0x00000150) #define FEC0_RDSR (FEC_REG_BASE + 0x00000180) #define FEC0_TDSR (FEC_REG_BASE + 0x00000184) #define FEC0_MRBR (FEC_REG_BASE + 0x00000188) /* ----------------------------------------------------------------------------- */ /* FEC1 */ /* ----------------------------------------------------------------------------- */ #define FEC1_IR (FEC1_REG_BASE + 0x00000004) #define FEC1_IMR (FEC1_REG_BASE + 0x00000008) #define FEC1_RDAR (FEC1_REG_BASE + 0x00000010) #define FEC1_TDAR (FEC1_REG_BASE + 0x00000014) #define FEC1_ECR (FEC1_REG_BASE + 0x00000024) #define FEC1_MMFR (FEC1_REG_BASE + 0x00000040) #define FEC1_MSCR (FEC1_REG_BASE + 0x00000044) #define FEC1_MIBCR (FEC1_REG_BASE + 0x00000064) #define FEC1_RCR (FEC1_REG_BASE + 0x00000084) #define FEC1_TCR (FEC1_REG_BASE + 0x000000C4) #define FEC1_PALR (FEC1_REG_BASE + 0x000000E4) #define FEC1_PAHR (FEC1_REG_BASE + 0x000000E8) #define FEC1_OPDR (FEC1_REG_BASE + 0x000000EC) #define FEC1_IHTUR (FEC1_REG_BASE + 0x00000118) #define FEC1_IHTLR (FEC1_REG_BASE + 0x0000011C) #define FEC1_GHTUR (FEC1_REG_BASE + 0x00000120) #define FEC1_GHTLR (FEC1_REG_BASE + 0x00000124) #define FEC1_TFWR (FEC1_REG_BASE + 0x00000144) #define FEC1_FRBR (FEC1_REG_BASE + 0x0000014C) #define FEC1_FRSAR (FEC1_REG_BASE + 0x00000150) #define FEC1_RDSR (FEC1_REG_BASE + 0x00000180) #define FEC1_TDSR (FEC1_REG_BASE + 0x00000184) #define FEC1_MRBR (FEC1_REG_BASE + 0x00000188) /* ------------------------------------- */ /* FEC_IR Register Bits */ #define FEC_IR_HBERR (0x80000000) #define FEC_IR_BABR (0x40000000) #define FEC_IR_BABT (0x20000000) #define FEC_IR_GRA (0x10000000) #define FEC_IR_TXF (0x08000000 ) #define FEC_IR_TXB (0x04000000 ) #define FEC_IR_RXF (0x02000000 ) #define FEC_IR_RXB (0x01000000 ) #define FEC_IR_MII (0x00800000 ) #define FEC_IR_EBERR (0x00400000) #define FEC_IR_LC (0x00200000 ) #define FEC_IR_RL (0x00100000 ) #define FEC_IR_UN (0x00080000 ) /* ------------------------------------- */ /* FEC_IMR Register Bits */ #define FEC_IR_HBERR_MASK (0x80000000) #define FEC_IR_BABR_MASK (0x40000000) #define FEC_IR_BABT_MASK (0x20000000) #define FEC_IR_GRA_MASK (0x10000000) #define FEC_IR_TXF_MASK (0x08000000 ) #define FEC_IR_TXB_MASK (0x04000000 ) #define FEC_IR_RXF_MASK (0x02000000 ) #define FEC_IR_RXB_MASK (0x01000000 ) #define FEC_IR_MII_MASK (0x00800000 ) #define FEC_IR_EBERR_MASK (0x00400000) #define FEC_IR_LC_MASK (0x00200000 ) #define FEC_IR_RL_MASK (0x00100000 ) #define FEC_IR_UN_MASK (0x00080000 ) /* ------------------------------------- */ /* FEC_RDAR Register Bits */ #define FEC_RDAR_RX_DES_ACTIVE (0x01000000) /* ------------------------------------- */ /* FEC_TDAR Register Bits */ #define FEC_TDAR_TX_DES_ACTIVE (0x01000000) /* ------------------------------------- */ /* FEC_ECR Register Bits */ #define FEC_ECR_ETHER_EN (0xF0000002) #define FEC_ECR_RESET (0xF0000001) /* ------------------------------------- */ /* FEC_MIBCR Register Bits */ #define FEC_MIBCR_MIB_DISABLE (0x10000000) #define FEC_MIBCR_MIB_IDLE (0x01000000) /* ------------------------------------- */ /* FEC_RCR Register Bits */ #define FEC_RCR_FCE (0x00000020) #define FEC_RCR_BC_REJ (0x00000010) #define FEC_RCR_PROM (0x00000008) #define FEC_RCR_MII_MODE (0x00000004) #define FEC_RCR_DRT (0x00000002) #define FEC_RCR_LOOP (0x00000001) /* ------------------------------------- */ /* FEC_TCR Register Bits */ #define FEC_TCR_RFC_PAUSE (0x00000010) #define FEC_TCR_TFC_PAUSE (0x00000008) #define FEC_TCR_FDEN (0x00000004) #define FEC_TCR_HBC (0x00000002) #define FEC_TCR_GTS (0x00000001) /* ----------------------------------------------------------------------------- */ /* Timers */ /* ----------------------------------------------------------------------------- */ #define TIM0_DTMR (TIMER0_BASE + 0x00000000) #define TIM0_DTXMR (TIMER0_BASE + 0x00000002) #define TIM0_DTER (TIMER0_BASE + 0x00000003) #define TIM0_DTRR (TIMER0_BASE + 0x00000004) #define TIM0_DTCR ⌨️ 快捷键说明
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