📄 mem_map.h
字号:
#define RESERVED_134 (134) #define RESERVED_135 (135) #define RESERVED_136 (136) #define RESERVED_137 (137) #define RESERVED_138 (138) #define RESERVED_139 (139) #define RESERVED_140 (140) #define RESERVED_141 (141) #define RESERVED_142 (142) #define RESERVED_143 (143) #define RESERVED_144 (144) #define RESERVED_145 (145) #define RESERVED_146 (146) #define RESERVED_147 (147 ) #define RESERVED_148 (148) #define RESERVED_149 (149) #define RESERVED_150 (150) #define RESERVED_151 (151) #define RESERVED_152 (152) #define RESERVED_153 (153) #define RESERVED_154 (154) #define RESERVED_155 (155) #define RESERVED_156 (156) #define RESERVED_157 (157) #define RESERVED_158 (158) #define RESERVED_159 (159) #define RESERVED_160 (160) #define DSPI_EOQF_INT (161) #define DSPI_TFFF_INT (162) #define DSPI_TCF_INT (163) #define DSPI_TFUF_INT (164) #define DSPI_RFDF_INT (165) #define DSPI_RFOF_INT (166) #define DSPI_OVERRUN_INT (167) #define RNGA_INT (168) #define RESERVED_169 (169) #define RESERVED_170 (170) #define PIT0_INT (171) #define PIT1_INT (172) #define PIT2_INT (173) #define PIT3_INT (174) #define USB_OTG_INT (175) #define RESERVED_176 (176) #define SSI_INT (177) #define RESERVED_178 (178) #define RESERVED_179 (179) #define RESERVED_180 (180) /* define RTC_INT 180 */#define CIM_OTG_INT (181) #define ATA_INT (182) #define PCI_INT (183) #define PCI_ARB_INT (184) #define PLL_LOL_INT (185) #define RESERVED_186 (186) #define RESERVED_187 (187) #define RESERVED_188 (188) #define RESERVED_189 (189) #define RESERVED_190 (190) #define RESERVED_191 (191) /* ----------------------------------------------------------------------------- */ /* Module scratch space defines (32k per define) */ /* ----------------------------------------------------------------------------- */ #define SCRATCH_BASE (CS1_BASE) #define TRIGGER_SCRATCH (SCRATCH_BASE + 0x00000000) #define CIM_SCRATCH (SCRATCH_BASE + 0x00008000) #define DEBUG_SCRATCH (SCRATCH_BASE + 0x00010000) #define DMA_SCRATCH (SCRATCH_BASE + 0x00018000) #define EPORT_SCRATCH (SCRATCH_BASE + 0x00020000) #define FEC0_SCRATCH (SCRATCH_BASE + 0x00028000) #define FLEXBUS_SCRATCH (SCRATCH_BASE + 0x00030000) #define ATA_SCRATCH (SCRATCH_BASE + 0x00038000) #define I2C_SCRATCH (SCRATCH_BASE + 0x00040000) #define PIT0_SCRATCH (SCRATCH_BASE + 0x00050000) #define PIT1_SCRATCH (SCRATCH_BASE + 0x00058000) #define PIT2_SCRATCH (SCRATCH_BASE + 0x00060000) #define PIT3_SCRATCH (SCRATCH_BASE + 0x00068000) #define PLL_SCRATCH (SCRATCH_BASE + 0x00070000) #define DSPI_SCRATCH (SCRATCH_BASE + 0x00078000) #define RTC_SCRATCH (SCRATCH_BASE + 0x00080000) #define SDRAMC_SCRATCH (SCRATCH_BASE + 0x00088000) #define SSI_SCRATCH (SCRATCH_BASE + 0x00090000) #define TIM0_SCRATCH (SCRATCH_BASE + 0x00098000) #define TIM1_SCRATCH (SCRATCH_BASE + 0x000A0000) #define TIM2_SCRATCH (SCRATCH_BASE + 0x000A8000) #define TIM3_SCRATCH (SCRATCH_BASE + 0x000B0000) #define UART0_SCRATCH (SCRATCH_BASE + 0x000B8000) #define UART1_SCRATCH (SCRATCH_BASE + 0x000C0000) #define UART2_SCRATCH (SCRATCH_BASE + 0x000C8000) #define USB_OTG_SCRATCH (SCRATCH_BASE + 0x000D8000) #define FEC1_SCRATCH (SCRATCH_BASE + 0x000E0000) #define RNGA_SCRATCH (SCRATCH_BASE + 0x000F8000) /* ----------------------------------------------------------------------------- */ /* KRAM space defines (2k per define) */ /* ----------------------------------------------------------------------------- */ #define KRAM_SLOT00 (KRAM_BASE + SIZE_2K*0) #define KRAM_SLOT01 (KRAM_BASE + SIZE_2K*1) #define KRAM_SLOT02 (KRAM_BASE + SIZE_2K*2) #define KRAM_SLOT03 (KRAM_BASE + SIZE_2K*3) #define KRAM_SLOT04 (KRAM_BASE + SIZE_2K*4) #define KRAM_SLOT05 (KRAM_BASE + SIZE_2K*5) #define KRAM_SLOT06 (KRAM_BASE + SIZE_2K*6) #define KRAM_SLOT07 (KRAM_BASE + SIZE_2K*7) #define KRAM_SLOT08 (KRAM_BASE + SIZE_2K*8) #define KRAM_SLOT09 (KRAM_BASE + SIZE_2K*9) #define KRAM_SLOT10 (KRAM_BASE + SIZE_2K*10) #define KRAM_SLOT11 (KRAM_BASE + SIZE_2K*11) #define KRAM_SLOT12 (KRAM_BASE + SIZE_2K*12) #define KRAM_SLOT13 (KRAM_BASE + SIZE_2K*13) #define KRAM_SLOT14 (KRAM_BASE + SIZE_2K*14) #define KRAM_SLOT15 (KRAM_BASE + SIZE_2K*15) /* ----------------------------------------------------------------------------- */ /* SDRAM space defines (4M per define) */ /* ----------------------------------------------------------------------------- */ #define SDRAM_SLOT00 (SDRAMC_BASE + SIZE_4M*0) #define SDRAM_SLOT01 (SDRAMC_BASE + SIZE_4M*1) #define SDRAM_SLOT02 (SDRAMC_BASE + SIZE_4M*2) #define SDRAM_SLOT03 (SDRAMC_BASE + SIZE_4M*3) #define SDRAM_SLOT04 (SDRAMC_BASE + SIZE_4M*4) #define SDRAM_SLOT05 (SDRAMC_BASE + SIZE_4M*5) #define SDRAM_SLOT06 (SDRAMC_BASE + SIZE_4M*6) #define SDRAM_SLOT07 (SDRAMC_BASE + SIZE_4M*7) #define SDRAM_SLOT08 (SDRAMC_BASE + SIZE_4M*8) #define SDRAM_SLOT09 (SDRAMC_BASE + SIZE_4M*9) #define SDRAM_SLOT10 (SDRAMC_BASE + SIZE_4M*10) #define SDRAM_SLOT11 (SDRAMC_BASE + SIZE_4M*11) #define SDRAM_SLOT12 (SDRAMC_BASE + SIZE_4M*12) #define SDRAM_SLOT13 (SDRAMC_BASE + SIZE_4M*13) #define SDRAM_SLOT14 (SDRAMC_BASE + SIZE_4M*14) #define SDRAM_SLOT15 (SDRAMC_BASE + SIZE_4M*15) /* ----------------------------------------------------------------------------- */ /* FlexBus Registers */ /* ----------------------------------------------------------------------------- */ #define FLEXBUS_CSAR0 (FLEXBUS_REG_BASE + 0x00) #define FLEXBUS_CSMR0 (FLEXBUS_REG_BASE + 0x04) #define FLEXBUS_CSCR0 (FLEXBUS_REG_BASE + 0x08) #define FLEXBUS_CSAR1 (FLEXBUS_REG_BASE + 0x0C) #define FLEXBUS_CSMR1 (FLEXBUS_REG_BASE + 0x10) #define FLEXBUS_CSCR1 (FLEXBUS_REG_BASE + 0x14) #define FLEXBUS_CSAR2 (FLEXBUS_REG_BASE + 0x18) #define FLEXBUS_CSMR2 (FLEXBUS_REG_BASE + 0x1C) #define FLEXBUS_CSCR2 (FLEXBUS_REG_BASE + 0x20) #define FLEXBUS_CSAR3 (FLEXBUS_REG_BASE + 0x24) #define FLEXBUS_CSMR3 (FLEXBUS_REG_BASE + 0x28) #define FLEXBUS_CSCR3 (FLEXBUS_REG_BASE + 0x2C) #define FLEXBUS_CSAR4 (FLEXBUS_REG_BASE + 0x30) #define FLEXBUS_CSMR4 (FLEXBUS_REG_BASE + 0x34) #define FLEXBUS_CSCR4 (FLEXBUS_REG_BASE + 0x38) #define FLEXBUS_CSAR5 (FLEXBUS_REG_BASE + 0x3C) #define FLEXBUS_CSMR5 (FLEXBUS_REG_BASE + 0x40) #define FLEXBUS_CSCR5 (FLEXBUS_REG_BASE + 0x44) /* ----------------------------------------------------------------------------- */ /* Testbench stuff */ /* ----------------------------------------------------------------------------- */ #define CS0_BASE (FLEXBUS_BASE) #define CS1_BASE (FLEXBUS_BASE2) #define CS2_BASE (CS1_BASE + SIZE_16M) #define CS3_BASE (CS2_BASE + SIZE_16M) #define CS0_SIZE (SIZE_4M) #define CS1_SIZE (SIZE_1M) #define CS2_SIZE (SIZE_16M) #define CS3_SIZE (SIZE_64K) /* CPRINT addresses */#define PH_BASE (CS1_BASE) #define PH_EXIT (PH_BASE + 0x40) #define CPRINT_CMD (PH_BASE + 0x44) #define CPRINT_ARG0 (PH_BASE + 0x48) #define CPRINT_ARG1 (PH_BASE + 0x4C) #define CPRINT_ARG2 (PH_BASE + 0x50) #define CPRINT_ARG3 (PH_BASE + 0x54) #define CPRINT_ARG4 (PH_BASE + 0x58) /* Pass/Fail values */#define PH_PASS (0x0FACE0FF) #define PH_FAIL (0x1FACE0FF) /* Vera <-> C coordination */#define VERA_EXIT_WORD (KRAM_BASE + KRAM_SIZE - 4) #define VERA_START_DATA (0x01234567) #define VERA_C_START_DATA (0x00000000) #define VERA_DONE_DATA (0xffffffff) /* Vera -> C commands */#define VERA_COMMAND_WORD (KRAM_BASE + KRAM_SIZE - 8) #define VERA_DDR216_DATA (0x00000001) #define VERA_SDR16_DATA (0x00000002) #define VERA_DDR16_DATA (0x00000003) #define VERA_SKIP_MAIN_LOOP_C_DATA (0x00000004) #define VERA_C_PCI_INT (0x00000005) /* Vera -> C random data */#define VERA_RANDOM_WORD (KRAM_BASE + KRAM_SIZE - 12) /* C -> Vera KRAM address for interrupt counters */#define VERA_CNT_BASE (KRAM_BASE + KRAM_SIZE - 4*256) #define VERA_CNT_INT_RESET_SP (VERA_CNT_BASE + 4*0) #define VERA_CNT_INT_RESET_PC (VERA_CNT_BASE + 4*1) #define VERA_CNT_INT_ACCESS_ERROR (VERA_CNT_BASE + 4*2) #define VERA_CNT_INT_ADDRESS_ERROR (VERA_CNT_BASE + 4*3) #define VERA_CNT_INT_ILLEGAL_INSTRUCTION (VERA_CNT_BASE + 4*4) #define VERA_CNT_INT_DIVIDE_BY_ZERO (VERA_CNT_BASE + 4*5) #define VERA_CNT_INT_PRIVILEGE_VIOLATION (VERA_CNT_BASE + 4*8) #define VERA_CNT_INT_INSTRUCTION_TRACE (VERA_CNT_BASE + 4*9) #define VERA_CNT_INT_UNIMPLEMENTED_LINE_A_OPCODE (VERA_CNT_BASE + 4*10) #define VERA_CNT_INT_UNIMPLEMENTED_LINE_F_OPCODE (VERA_CNT_BASE + 4*11) #define VERA_CNT_INT_DEBUG_INTERRUPT (VERA_CNT_BASE + 4*12) #define VERA_CNT_INT_RTE_FORMAT_ERROR (VERA_CNT_BASE + 4*14) #define VERA_CNT_INT_UNINITIALIZED_INTERRUPT (VERA_CNT_BASE + 4*15) #define VERA_CNT_INT_SPURIOUS_INTERRUPT (VERA_CNT_BASE + 4*24) #define VERA_CNT_INT_TRAP0 (VERA_CNT_BASE + 4*32) #define VERA_CNT_INT_TRAP1 (VERA_CNT_BASE + 4*33) #define VERA_CNT_INT_TRAP2 (VERA_CNT_BASE + 4*34) #define VERA_CNT_INT_TRAP3 (VERA_CNT_BASE + 4*35) #define VERA_CNT_INT_TRAP4 (VERA_CNT_BASE + 4*36) #define VERA_CNT_INT_TRAP5 (VERA_CNT_BASE + 4*37) #define VERA_CNT_INT_TRAP6 (VERA_CNT_BASE + 4*38) #define VERA_CNT_INT_TRAP7 (VERA_CNT_BASE + 4*39) #define VERA_CNT_INT_TRAP8 (VERA_CNT_BASE + 4*40) #define VERA_CNT_INT_TRAP9 (VERA_CNT_BASE + 4*41) #define VERA_CNT_INT_TRAP10 (VERA_CNT_BASE + 4*42) #define VERA_CNT_INT_TRAP11 (VERA_CNT_BASE + 4*43) #define VERA_CNT_INT_TRAP12 (VERA_CNT_BASE + 4*44) #define VERA_CNT_INT_TRAP13 (VERA_CNT_BASE + 4*45) #define VERA_CNT_INT_TRAP14 (VERA_CNT_BASE + 4*46) #define VERA_CNT_INT_TRAP15 (VERA_CNT_BASE + 4*47) #define VERA_CNT_INT_UNSUPPORTED_INSTRUCTION (VERA_CNT_BASE + 4*61) #define VERA_CNT_RESERVED_1 (VERA_CNT_BASE + 4*64) #define VERA_CNT_EPORT_INT_1 (VERA_CNT_BASE + 4*65) #define VERA_CNT_EPORT_INT_2 (VERA_CNT_BASE + 4*66) #define VERA_CNT_EPORT_INT_3 (VERA_CNT_BASE + 4*67) #define VERA_CNT_EPORT_INT_4 (VERA_CNT_BASE + 4*68) #define VERA_CNT_EPORT_INT_5 (VERA_CNT_BASE + 4*69) #define VERA_CNT_EPORT_INT_6 (VERA_CNT_BASE + 4*70) #define VERA_CNT_EPORT_INT_7 (VERA_CNT_BASE + 4*71) #define VERA_CNT_DMA_INT_0 (VERA_CNT_BASE + 4*72) #define VERA_CNT_DMA_INT_1 (VERA_CNT_BASE + 4*73) #define VERA_CNT_DMA_INT_2 (VERA_CNT_BASE + 4*74) #define VERA_CNT_DMA_INT_3 (VERA_CNT_BASE + 4*75) #define VERA_CNT_DMA_INT_4 (VERA_CNT_BASE + 4*76) #define VERA_CNT_DMA_INT_5 (VERA_CNT_BASE + 4*77) #define VERA_CNT_DMA_INT_6 (VERA_CNT_BASE + 4*78) #define VERA_CNT_DMA_INT_7 (VERA_CNT_BASE + 4*79) #define VERA_CNT_DMA_INT_8 (VERA_CNT_BASE + 4*80) #define VERA_CNT_DMA_INT_9 (VERA_CNT_BASE + 4*81) #define VERA_CNT_DMA_INT_10 (VERA_CNT_BASE + 4*82) #define VERA_CNT_DMA_INT_11 (VERA_CNT_BASE + 4*83) #define VERA_CNT_DMA_INT_12 (VERA_CNT_BASE + 4*84) #define VERA_CNT_DMA_INT_13 (VERA_CNT_BASE + 4*85) #define VERA_CNT_DMA_INT_14 (VERA_CNT_BASE + 4*86) #define VERA_CNT_DMA_INT_15 (VERA_CNT_BASE + 4*87) #define VERA_CNT_DMA_ERROR_INT (VERA_CNT_BASE + 4*88) #define VERA_CNT_SWT_INT (VERA_CNT_BASE + 4*89) #define VERA_CNT_UART0_INT (VERA_CNT_BASE + 4*90) #define VERA_CNT_UART1_INT (VERA_CNT_BASE + 4*91) #define VERA_CNT_UART2_INT (VERA_CNT_BASE + 4*92) #define VERA_CNT_RESERVED_2 (VERA_CNT_BASE + 4*93) #define VERA_CNT_I2C_INT (VERA_CNT_BASE + 4*94) #define VERA_CNT_DSPI_INT (VERA_CNT_BASE + 4*95) #define VERA_CNT_TIMER0_INT (VERA_CNT_BASE + 4*96) #define VERA_CNT_TIMER1_INT (VERA_CNT_BASE + 4*97) #define VERA_CNT_TIMER2_INT (VERA_CNT_BASE + 4*98) #define VERA_CNT_TIMER3_INT (VERA_CNT_BASE + 4*99) #define VERA_CNT_FEC_X_INTF_INT (VERA_CNT_BASE + 4*100) #define VERA_CNT_FEC_X_INTB_INT (VERA_CNT_BASE + 4*101) #define VERA_CNT_FEC_UN_INT (VERA_CNT_BASE + 4*102) #define VERA_CNT_FEC_RL_INT (VERA_CNT_BASE + 4*103) #define VERA_CNT_FEC_R_INTF_INT (VERA_CNT_BASE + 4*104) #define VERA_CNT_FEC_R_INTB_INT (VERA_CNT_BASE + 4*105) #define VERA_CNT_FEC_MII_INT (VERA_CNT_BASE + 4*106) #define VERA_CNT_FEC_LC_INT (VERA_CNT_BASE + 4*107) ⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -