📄 mem_map.h
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#define INTC0_IMRL (INTC0_BASE + 0x0C) #define INTC0_INTFRCH (INTC0_BASE + 0x10) #define INTC0_INTFRCL (INTC0_BASE + 0x14) #define INTC0_ICONFIG (INTC0_BASE + 0x18) #define INTC0_MASKS (INTC0_BASE + 0x1C) #define INTC0_SIMR (INTC0_BASE + 0x1C) #define INTC0_CIMR (INTC0_BASE + 0x1D) #define INTC0_CLMASK (INTC0_BASE + 0x1E) #define INTC0_SLMASK (INTC0_BASE + 0x1F) #define ICR000 (INTC0_BASE + 0x40) #define ICR001 (INTC0_BASE + 0x41) #define ICR002 (INTC0_BASE + 0x42) #define ICR003 (INTC0_BASE + 0x43) #define ICR004 (INTC0_BASE + 0x44) #define ICR005 (INTC0_BASE + 0x45) #define ICR006 (INTC0_BASE + 0x46) #define ICR007 (INTC0_BASE + 0x47) #define ICR008 (INTC0_BASE + 0x48) #define ICR009 (INTC0_BASE + 0x49) #define ICR010 (INTC0_BASE + 0x4A) #define ICR011 (INTC0_BASE + 0x4B) #define ICR012 (INTC0_BASE + 0x4C) #define ICR013 (INTC0_BASE + 0x4D) #define ICR014 (INTC0_BASE + 0x4E) #define ICR015 (INTC0_BASE + 0x4F) #define ICR016 (INTC0_BASE + 0x50) #define ICR017 (INTC0_BASE + 0x51) #define ICR018 (INTC0_BASE + 0x52) #define ICR019 (INTC0_BASE + 0x53) #define ICR020 (INTC0_BASE + 0x54) #define ICR021 (INTC0_BASE + 0x55) #define ICR022 (INTC0_BASE + 0x56) #define ICR023 (INTC0_BASE + 0x57) #define ICR024 (INTC0_BASE + 0x58) #define ICR025 (INTC0_BASE + 0x59) #define ICR026 (INTC0_BASE + 0x5A) #define ICR027 (INTC0_BASE + 0x5B) #define ICR028 (INTC0_BASE + 0x5C) #define ICR029 (INTC0_BASE + 0x5D) #define ICR030 (INTC0_BASE + 0x5E) #define ICR031 (INTC0_BASE + 0x5F) #define ICR032 (INTC0_BASE + 0x60) #define ICR033 (INTC0_BASE + 0x61) #define ICR034 (INTC0_BASE + 0x62) #define ICR035 (INTC0_BASE + 0x63) #define ICR036 (INTC0_BASE + 0x64) #define ICR037 (INTC0_BASE + 0x65) #define ICR038 (INTC0_BASE + 0x66) #define ICR039 (INTC0_BASE + 0x67) #define ICR040 (INTC0_BASE + 0x68) #define ICR041 (INTC0_BASE + 0x69) #define ICR042 (INTC0_BASE + 0x6A) #define ICR043 (INTC0_BASE + 0x6B) #define ICR044 (INTC0_BASE + 0x6C) #define ICR045 (INTC0_BASE + 0x6D) #define ICR046 (INTC0_BASE + 0x6E) #define ICR047 (INTC0_BASE + 0x6F) #define ICR048 (INTC0_BASE + 0x70) #define ICR049 (INTC0_BASE + 0x71) #define ICR050 (INTC0_BASE + 0x72) #define ICR051 (INTC0_BASE + 0x73) #define ICR052 (INTC0_BASE + 0x74) #define ICR053 (INTC0_BASE + 0x75) #define ICR054 (INTC0_BASE + 0x76) #define ICR055 (INTC0_BASE + 0x77) #define ICR056 (INTC0_BASE + 0x78) #define ICR057 (INTC0_BASE + 0x79) #define ICR058 (INTC0_BASE + 0x7A) #define ICR059 (INTC0_BASE + 0x7B) #define ICR060 (INTC0_BASE + 0x7C) #define ICR061 (INTC0_BASE + 0x7D) #define ICR062 (INTC0_BASE + 0x7E) #define ICR063 (INTC0_BASE + 0x7F) #define INTC0_SWIACK (INTC0_BASE + 0xE0) #define INTC0_LVL1IACK (INTC0_BASE + 0xE4) #define INTC0_LVL2IACK (INTC0_BASE + 0xE8) #define INTC0_LVL3IACK (INTC0_BASE + 0xEC) #define INTC0_LVL4IACK (INTC0_BASE + 0xF0) #define INTC0_LVL5IACK (INTC0_BASE + 0xF4) #define INTC0_LVL6IACK (INTC0_BASE + 0xF8) #define INTC0_LVL7IACK (INTC0_BASE + 0xFC) #define INTC1_IPRH (INTC1_BASE + 0x00) #define INTC1_IPRL (INTC1_BASE + 0x04) #define INTC1_IMRH (INTC1_BASE + 0x08) #define INTC1_IMRL (INTC1_BASE + 0x0C) #define INTC1_INTFRCH (INTC1_BASE + 0x10) #define INTC1_INTFRCL (INTC1_BASE + 0x14) #define INTC1_ICONFIG (INTC1_BASE + 0x18) #define INTC1_MASKS (INTC1_BASE + 0x1C) #define INTC1_SIMR (INTC1_BASE + 0x1C) #define INTC1_CIMR (INTC1_BASE + 0x1D) #define INTC1_CLMASK (INTC1_BASE + 0x1E) #define INTC1_SLMASK (INTC1_BASE + 0x1F) #define ICR100 (INTC1_BASE + 0x40) #define ICR101 (INTC1_BASE + 0x41) #define ICR102 (INTC1_BASE + 0x42) #define ICR103 (INTC1_BASE + 0x43) #define ICR104 (INTC1_BASE + 0x44) #define ICR105 (INTC1_BASE + 0x45) #define ICR106 (INTC1_BASE + 0x46) #define ICR107 (INTC1_BASE + 0x47) #define ICR108 (INTC1_BASE + 0x48) #define ICR109 (INTC1_BASE + 0x49) #define ICR110 (INTC1_BASE + 0x4A) #define ICR111 (INTC1_BASE + 0x4B) #define ICR112 (INTC1_BASE + 0x4C) #define ICR113 (INTC1_BASE + 0x4D) #define ICR114 (INTC1_BASE + 0x4E) #define ICR115 (INTC1_BASE + 0x4F) #define ICR116 (INTC1_BASE + 0x50) #define ICR117 (INTC1_BASE + 0x51) #define ICR118 (INTC1_BASE + 0x52) #define ICR119 (INTC1_BASE + 0x53) #define ICR120 (INTC1_BASE + 0x54) #define ICR121 (INTC1_BASE + 0x55) #define ICR122 (INTC1_BASE + 0x56) #define ICR123 (INTC1_BASE + 0x57) #define ICR124 (INTC1_BASE + 0x58) #define ICR125 (INTC1_BASE + 0x59) #define ICR126 (INTC1_BASE + 0x5A) #define ICR127 (INTC1_BASE + 0x5B) #define ICR128 (INTC1_BASE + 0x5C) #define ICR129 (INTC1_BASE + 0x5D) #define ICR130 (INTC1_BASE + 0x5E) #define ICR131 (INTC1_BASE + 0x5F) #define ICR132 (INTC1_BASE + 0x60) #define ICR133 (INTC1_BASE + 0x61) #define ICR134 (INTC1_BASE + 0x62) #define ICR135 (INTC1_BASE + 0x63) #define ICR136 (INTC1_BASE + 0x64) #define ICR137 (INTC1_BASE + 0x65) #define ICR138 (INTC1_BASE + 0x66) #define ICR139 (INTC1_BASE + 0x67) #define ICR140 (INTC1_BASE + 0x68) #define ICR141 (INTC1_BASE + 0x69) #define ICR142 (INTC1_BASE + 0x6A) #define ICR143 (INTC1_BASE + 0x6B) #define ICR144 (INTC1_BASE + 0x6C) #define ICR145 (INTC1_BASE + 0x6D) #define ICR146 (INTC1_BASE + 0x6E) #define ICR147 (INTC1_BASE + 0x6F) #define ICR148 (INTC1_BASE + 0x70) #define ICR149 (INTC1_BASE + 0x71) #define ICR150 (INTC1_BASE + 0x72) #define ICR151 (INTC1_BASE + 0x73) #define ICR152 (INTC1_BASE + 0x74) #define ICR153 (INTC1_BASE + 0x75) #define ICR154 (INTC1_BASE + 0x76) #define ICR155 (INTC1_BASE + 0x77) #define ICR156 (INTC1_BASE + 0x78) #define ICR157 (INTC1_BASE + 0x79) #define ICR158 (INTC1_BASE + 0x7A) #define ICR159 (INTC1_BASE + 0x7B) #define ICR160 (INTC1_BASE + 0x7C) #define ICR161 (INTC1_BASE + 0x7D) #define ICR162 (INTC1_BASE + 0x7E) #define ICR163 (INTC1_BASE + 0x7F) #define INTC1_SWIACK (INTC1_BASE + 0xE0) #define INTC1_LVL1IACK (INTC1_BASE + 0xE4) #define INTC1_LVL2IACK (INTC1_BASE + 0xE8) #define INTC1_LVL3IACK (INTC1_BASE + 0xEC) #define INTC1_LVL4IACK (INTC1_BASE + 0xF0) #define INTC1_LVL5IACK (INTC1_BASE + 0xF4) #define INTC1_LVL6IACK (INTC1_BASE + 0xF8) #define INTC1_LVL7IACK (INTC1_BASE + 0xFC) /* ----------------------------------------------------------------------------- */ /* ColdFire V4 processor exceptions */ /* ----------------------------------------------------------------------------- */ #define INT_RESET_SP (0) #define INT_RESET_PC (1) #define INT_ACCESS_ERROR (2) #define INT_ADDRESS_ERROR (3) #define INT_ILLEGAL_INSTRUCTION (4) #define INT_DIVIDE_BY_ZERO (5) #define INT_PRIVILEGE_VIOLATION (8) #define INT_INSTRUCTION_TRACE (9) #define INT_UNIMPLEMENTED_LINE_A_OPCODE (10) #define INT_UNIMPLEMENTED_LINE_F_OPCODE (11) #define INT_DEBUG_INTERRUPT (12) #define INT_RTE_FORMAT_ERROR (14) #define INT_UNINITIALIZED_INTERRUPT (15) #define INT_SPURIOUS_INTERRUPT (24) #define INT_TRAP0 (32) #define INT_TRAP1 (33) #define INT_TRAP2 (34) #define INT_TRAP3 (35) #define INT_TRAP4 (36) #define INT_TRAP5 (37) #define INT_TRAP6 (38) #define INT_TRAP7 (39) #define INT_TRAP8 (40) #define INT_TRAP9 (41) #define INT_TRAP10 (42) #define INT_TRAP11 (43) #define INT_TRAP12 (44) #define INT_TRAP13 (45) #define INT_TRAP14 (46) #define INT_TRAP15 (47) #define INT_UNSUPPORTED_INSTRUCTION (61) /* ----------------------------------------------------------------------------- */ /* Redstripe interrupts requests connected to controller 0 */ /* ----------------------------------------------------------------------------- */ #define RESERVED_64 (64) #define EPORT_INT_1 (65) #define EPORT_INT_2 (66) #define EPORT_INT_3 (67) #define EPORT_INT_4 (68) #define EPORT_INT_5 (69) #define EPORT_INT_6 (70) #define EPORT_INT_7 (71) #define DMA_INT_0 (72) #define DMA_INT_1 (73) #define DMA_INT_2 (74) #define DMA_INT_3 (75) #define DMA_INT_4 (76) #define DMA_INT_5 (77) #define DMA_INT_6 (78) #define DMA_INT_7 (79) #define DMA_INT_8 (80) #define DMA_INT_9 (81) #define DMA_INT_10 (82) #define DMA_INT_11 (83) #define DMA_INT_12 (84) #define DMA_INT_13 (85) #define DMA_INT_14 (86) #define DMA_INT_15 (87) #define DMA_ERROR_INT (88) #define SWT_INT (89) #define UART0_INT (90) #define UART1_INT (91) #define UART2_INT (92) #define RESERVED_2 (93) #define I2C_INT (94) #define DSPI_INT (95) #define TIMER0_INT (96) #define TIMER1_INT (97) #define TIMER2_INT (98) #define TIMER3_INT (99) #define FEC0_X_INTF_INT (100) #define FEC0_X_INTB_INT (101) #define FEC0_UN_INT (102) #define FEC0_RL_INT (103) #define FEC0_R_INTF_INT (104) #define FEC0_R_INTB_INT (105) #define FEC0_MII_INT (106) #define FEC0_LC_INT (107) #define FEC0_HBERR_INT (108) #define FEC0_GRA_INT (109) #define FEC0_EBERR_INT (110) #define FEC0_BABT_INT (111) #define FEC0_BABR_INT (112) #define FEC1_X_INTF_INT (113) #define FEC1_X_INTB_INT (114) #define FEC1_UN_INT (115) #define FEC1_RL_INT (116) #define FEC1_R_INTF_INT (117) #define FEC1_R_INTB_INT (118) #define FEC1_MII_INT (119) #define FEC1_LC_INT (120) #define FEC1_HBERR_INT (121) #define FEC1_GRA_INT (122) #define FEC1_EBERR_INT (123) #define FEC1_BABT_INT (124) #define FEC1_BABR_INT (125) #define MCM_BERR_INT (126) /* define RESERVED_127 127 */#define RTC_INT (127) /* ----------------------------------------------------------------------------- */ /* Redstripe interrupts requests connected to controller 1 */ /* ----------------------------------------------------------------------------- */ #define RESERVED_128 (128) #define RESERVED_129 (129) #define RESERVED_130 (130) #define RESERVED_131 (131) #define RESERVED_132 (132) #define RESERVED_133 (133) ⌨️ 快捷键说明
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