📄 mem_map.h
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#ifndef _MEM_MAP_H_#define _MEM_MAP_H_ /* ----------------------------------------------------------------------------- */ /* Useful constants */ /* ----------------------------------------------------------------------------- */ #define SIZE_1 (0x00000001) #define SIZE_2 (0x00000002) #define SIZE_4 (0x00000004) #define SIZE_8 (0x00000008) #define SIZE_16 (0x00000010) #define SIZE_32 (0x00000020) #define SIZE_64 (0x00000040) #define SIZE_128 (0x00000080) #define SIZE_256 (0x00000100) #define SIZE_512 (0x00000200) #define SIZE_1K (0x00000400) #define SIZE_2K (0x00000800) #define SIZE_4K (0x00001000) #define SIZE_8K (0x00002000) #define SIZE_16K (0x00004000) #define SIZE_32K (0x00008000) #define SIZE_64K (0x00010000) #define SIZE_128K (0x00020000) #define SIZE_256K (0x00040000) #define SIZE_512K (0x00080000) #define SIZE_1M (0x00100000) #define SIZE_2M (0x00200000) #define SIZE_4M (0x00400000) #define SIZE_8M (0x00800000) #define SIZE_16M (0x01000000) #define SIZE_32M (0x02000000) #define SIZE_64M (0x04000000) #define SIZE_128M (0x08000000) #define SIZE_256M (0x10000000) #define SIZE_512M (0x20000000) #define SIZE_1G (0x40000000) #define SIZE_2G (0x80000000) /* ----------------------------------------------------------------------------- */ /* AMBA Crossbar Slave Addresses */ /* ----------------------------------------------------------------------------- */ #define AXBS_SLAVE1 (0x00000000) #define AXBS_SLAVE1_2 (0xC0000000) #define AXBS_SLAVE2 (0x40000000) #define AXBS_SLAVE3 (0x90000000) #define AXBS_SLAVE4 (0x80000000) #define AXBS_SLAVE5 (0xA0000000) #define AXBS_SLAVE6 (0xE0000000) #define AXBS_SLAVE7 (0xF0000000) /* ----------------------------------------------------------------------------- */ /* SoC Slave Addresses */ /* ----------------------------------------------------------------------------- */ #define FLEXBUS_BASE (AXBS_SLAVE1) #define SDRAMC_BASE (AXBS_SLAVE2) #define ATA_BASE (AXBS_SLAVE3) #define KRAM_BASE (AXBS_SLAVE4) #define FLEXBUS_BASE2 (AXBS_SLAVE1_2) #define PCI_SLAVE_BASE (AXBS_SLAVE5) #define AIPS1_BASE (AXBS_SLAVE6 + 0x0C000000) #define AIPS0_BASE (AXBS_SLAVE7 + 0x0C000000) #define KRAM_SIZE (SIZE_32K) /* ----------------------------------------------------------------------------- */ /* AIPS Module Offsets */ /* ----------------------------------------------------------------------------- */ /* On-platform modules */#define AIPS_MOD00_OFFSET (0x00000000) #define AIPS_MOD01_OFFSET (0x00004000) #define AIPS_MOD02_OFFSET (0x00008000) #define AIPS_MOD03_OFFSET (0x0000C000) #define AIPS_MOD04_OFFSET (0x00010000) #define AIPS_MOD05_OFFSET (0x00014000) #define AIPS_MOD06_OFFSET (0x00018000) #define AIPS_MOD07_OFFSET (0x0001C000) #define AIPS_MOD08_OFFSET (0x00020000) #define AIPS_MOD09_OFFSET (0x00024000) #define AIPS_MOD10_OFFSET (0x00028000) #define AIPS_MOD11_OFFSET (0x0002C000) #define AIPS_MOD12_OFFSET (0x00030000) #define AIPS_MOD13_OFFSET (0x00034000) #define AIPS_MOD14_OFFSET (0x00038000) #define AIPS_MOD15_OFFSET (0x0003C000) #define AIPS_MOD16_OFFSET (0x00040000) #define AIPS_MOD17_OFFSET (0x00044000) #define AIPS_MOD18_OFFSET (0x00048000) #define AIPS_MOD19_OFFSET (0x0004C000) #define AIPS_MOD20_OFFSET (0x00050000) #define AIPS_MOD21_OFFSET (0x00054000) #define AIPS_MOD22_OFFSET (0x00058000) #define AIPS_MOD23_OFFSET (0x0005C000) #define AIPS_MOD24_OFFSET (0x00060000) #define AIPS_MOD25_OFFSET (0x00064000) #define AIPS_MOD26_OFFSET (0x00068000) #define AIPS_MOD27_OFFSET (0x0006C000) #define AIPS_MOD28_OFFSET (0x00070000) #define AIPS_MOD29_OFFSET (0x00074000) #define AIPS_MOD30_OFFSET (0x00078000) #define AIPS_MOD31_OFFSET (0x0007C000) /* Off-platform modules */#define AIPS_MOD32_OFFSET (0x00080000) #define AIPS_MOD33_OFFSET (0x00084000) #define AIPS_MOD34_OFFSET (0x00088000) #define AIPS_MOD35_OFFSET (0x0008C000) #define AIPS_MOD36_OFFSET (0x00090000) #define AIPS_MOD37_OFFSET (0x00094000) #define AIPS_MOD38_OFFSET (0x00098000) #define AIPS_MOD39_OFFSET (0x0009C000) #define AIPS_MOD40_OFFSET (0x000A0000) #define AIPS_MOD41_OFFSET (0x000A4000) #define AIPS_MOD42_OFFSET (0x000A8000) #define AIPS_MOD43_OFFSET (0x000AC000) #define AIPS_MOD44_OFFSET (0x000B0000) #define AIPS_MOD45_OFFSET (0x000B4000) #define AIPS_MOD46_OFFSET (0x000B8000) #define AIPS_MOD47_OFFSET (0x000BC000) #define AIPS_MOD48_OFFSET (0x000C0000) #define AIPS_MOD49_OFFSET (0x000C4000) #define AIPS_MOD50_OFFSET (0x000C8000) #define AIPS_MOD51_OFFSET (0x000CC000) #define AIPS_MOD52_OFFSET (0x000D0000) #define AIPS_MOD53_OFFSET (0x000D4000) #define AIPS_MOD54_OFFSET (0x000D8000) #define AIPS_MOD55_OFFSET (0x000DC000) #define AIPS_MOD56_OFFSET (0x000E0000) #define AIPS_MOD57_OFFSET (0x000E4000) #define AIPS_MOD58_OFFSET (0x000E8000) #define AIPS_MOD59_OFFSET (0x000EC000) #define AIPS_MOD60_OFFSET (0x000F0000) #define AIPS_MOD61_OFFSET (0x000F4000) #define AIPS_MOD62_OFFSET (0x000F8000) #define AIPS_MOD63_OFFSET (0x000FC000) /* ----------------------------------------------------------------------------- */ /* AIPS0 Slave Addresses */ /* ----------------------------------------------------------------------------- */ #define AIPS0_REG_BASE (AIPS0_BASE + AIPS_MOD00_OFFSET) #define AXBS_BASE (AIPS0_BASE + AIPS_MOD01_OFFSET) #define FLEXBUS_REG_BASE (AIPS0_BASE + AIPS_MOD02_OFFSET) #define FEC_REG_BASE (AIPS0_BASE + AIPS_MOD12_OFFSET) #define FEC1_REG_BASE (AIPS0_BASE + AIPS_MOD13_OFFSET) #define RTC_BASE (AIPS0_BASE + AIPS_MOD15_OFFSET) #define MCM_BASE (AIPS0_BASE + AIPS_MOD16_OFFSET) #define DMA2_BASE (AIPS0_BASE + AIPS_MOD17_OFFSET) #define INTC0_BASE (AIPS0_BASE + AIPS_MOD18_OFFSET) #define INTC1_BASE (AIPS0_BASE + AIPS_MOD19_OFFSET) #define INTC_IACK_BASE (AIPS0_BASE + AIPS_MOD21_OFFSET) #define I2C_BASE (AIPS0_BASE + AIPS_MOD22_OFFSET) #define DSPI_BASE (AIPS0_BASE + AIPS_MOD23_OFFSET) #define UART0_BASE (AIPS0_BASE + AIPS_MOD24_OFFSET) #define UART1_BASE (AIPS0_BASE + AIPS_MOD25_OFFSET) #define UART2_BASE (AIPS0_BASE + AIPS_MOD26_OFFSET) #define TIMER0_BASE (AIPS0_BASE + AIPS_MOD28_OFFSET) #define TIMER1_BASE (AIPS0_BASE + AIPS_MOD29_OFFSET) #define TIMER2_BASE (AIPS0_BASE + AIPS_MOD30_OFFSET) #define TIMER3_BASE (AIPS0_BASE + AIPS_MOD31_OFFSET) #define PIT0_BASE (AIPS0_BASE + AIPS_MOD32_OFFSET) #define PIT1_BASE (AIPS0_BASE + AIPS_MOD33_OFFSET) #define PIT2_BASE (AIPS0_BASE + AIPS_MOD34_OFFSET) #define PIT3_BASE (AIPS0_BASE + AIPS_MOD35_OFFSET) #define EPORT_BASE (AIPS0_BASE + AIPS_MOD37_OFFSET) #define WDT_BASE (AIPS0_BASE + AIPS_MOD38_OFFSET) #define CIM_BASE (AIPS0_BASE + AIPS_MOD40_OFFSET) #define PORTS_BASE (AIPS0_BASE + AIPS_MOD41_OFFSET) #define PCI_BASE (AIPS0_BASE + AIPS_MOD42_OFFSET) #define PCI_ARB_BASE (AIPS0_BASE + AIPS_MOD43_OFFSET) #define USB_OTG_BASE (AIPS0_BASE + AIPS_MOD44_OFFSET) #define RNGA_BASE (AIPS0_BASE + AIPS_MOD45_OFFSET) #define SDRAMC_REG_BASE (AIPS0_BASE + AIPS_MOD46_OFFSET) #define SSI_BASE (AIPS0_BASE + AIPS_MOD47_OFFSET) #define PLL_BASE (AIPS0_BASE + AIPS_MOD49_OFFSET) /* ----------------------------------------------------------------------------- */ /* AIPS1 Slave Addresses */ /* ----------------------------------------------------------------------------- */ /* define AIPS1_REG_BASE AIPS1_BASE + AIPS_MOD00_OFFSET */ /* ----------------------------------------------------------------------------- */ /* AIPS Registers */ /* ----------------------------------------------------------------------------- */ #define AIPS0_MPROT0_1 (AIPS0_REG_BASE + 0x00) #define AIPS0_MPROT2_3 (AIPS0_REG_BASE + 0x01) #define AIPS0_MPROT4_5 (AIPS0_REG_BASE + 0x02) #define AIPS0_MPROT6_7 (AIPS0_REG_BASE + 0x03) #define AIPS0_PACR0_1 (AIPS0_REG_BASE + 0x20) #define AIPS0_PACR2_3 (AIPS0_REG_BASE + 0x21) #define AIPS0_PACR4_5 (AIPS0_REG_BASE + 0x22) #define AIPS0_PACR6_7 (AIPS0_REG_BASE + 0x23) #define AIPS0_PACR8_9 (AIPS0_REG_BASE + 0x24) #define AIPS0_PACR10_11 (AIPS0_REG_BASE + 0x25) #define AIPS0_PACR12_13 (AIPS0_REG_BASE + 0x26) #define AIPS0_PACR14_15 (AIPS0_REG_BASE + 0x27) #define AIPS0_PACR16_17 (AIPS0_REG_BASE + 0x28) #define AIPS0_PACR18_19 (AIPS0_REG_BASE + 0x29) #define AIPS0_PACR20_21 (AIPS0_REG_BASE + 0x2a) #define AIPS0_PACR22_23 (AIPS0_REG_BASE + 0x2b) #define AIPS0_PACR24_25 (AIPS0_REG_BASE + 0x2c) #define AIPS0_PACR26_27 (AIPS0_REG_BASE + 0x2d) #define AIPS0_PACR28_29 (AIPS0_REG_BASE + 0x2e) #define AIPS0_PACR30_31 (AIPS0_REG_BASE + 0x2f) #define AIPS0_OPACR0_1 (AIPS0_REG_BASE + 0x40) #define AIPS0_OPACR2_3 (AIPS0_REG_BASE + 0x41) #define AIPS0_OPACR4_5 (AIPS0_REG_BASE + 0x42) #define AIPS0_OPACR6_7 (AIPS0_REG_BASE + 0x43) #define AIPS0_OPACR8_9 (AIPS0_REG_BASE + 0x44) #define AIPS0_OPACR10_11 (AIPS0_REG_BASE + 0x45) #define AIPS0_OPACR12_13 (AIPS0_REG_BASE + 0x46) #define AIPS0_OPACR14_15 (AIPS0_REG_BASE + 0x47) #define AIPS0_OPACR16_17 (AIPS0_REG_BASE + 0x48) #define AIPS0_OPACR18_19 (AIPS0_REG_BASE + 0x49) #define AIPS0_OPACR20_21 (AIPS0_REG_BASE + 0x4a) #define AIPS0_OPACR22_23 (AIPS0_REG_BASE + 0x4b) #define AIPS0_OPACR24_25 (AIPS0_REG_BASE + 0x4c) #define AIPS0_OPACR26_27 (AIPS0_REG_BASE + 0x4d) #define AIPS0_OPACR28_29 (AIPS0_REG_BASE + 0x4e) #define AIPS0_OPACR30_31 (AIPS0_REG_BASE + 0x4f) #define AIPS1_MPROT0_1 (AIPS1_REG_BASE + 0x00) #define AIPS1_MPROT2_3 (AIPS1_REG_BASE + 0x01) #define AIPS1_MPROT4_5 (AIPS1_REG_BASE + 0x02) #define AIPS1_MPROT6_7 (AIPS1_REG_BASE + 0x03) #define AIPS1_PACR0_1 (AIPS1_REG_BASE + 0x20) #define AIPS1_PACR2_3 (AIPS1_REG_BASE + 0x21) #define AIPS1_PACR4_5 (AIPS1_REG_BASE + 0x22) #define AIPS1_PACR6_7 (AIPS1_REG_BASE + 0x23) #define AIPS1_PACR8_9 (AIPS1_REG_BASE + 0x24) #define AIPS1_PACR10_11 (AIPS1_REG_BASE + 0x25) #define AIPS1_PACR12_13 (AIPS1_REG_BASE + 0x26) #define AIPS1_PACR14_15 (AIPS1_REG_BASE + 0x27) #define AIPS1_PACR16_17 (AIPS1_REG_BASE + 0x28) #define AIPS1_PACR18_19 (AIPS1_REG_BASE + 0x29) #define AIPS1_PACR20_21 (AIPS1_REG_BASE + 0x2a) #define AIPS1_PACR22_23 (AIPS1_REG_BASE + 0x2b) #define AIPS1_PACR24_25 (AIPS1_REG_BASE + 0x2c) #define AIPS1_PACR26_27 (AIPS1_REG_BASE + 0x2d) #define AIPS1_PACR28_29 (AIPS1_REG_BASE + 0x2e) #define AIPS1_PACR30_31 (AIPS1_REG_BASE + 0x2f) #define AIPS1_OPACR0_1 (AIPS1_REG_BASE + 0x40) #define AIPS1_OPACR2_3 (AIPS1_REG_BASE + 0x41) #define AIPS1_OPACR4_5 (AIPS1_REG_BASE + 0x42) #define AIPS1_OPACR6_7 (AIPS1_REG_BASE + 0x43) #define AIPS1_OPACR8_9 (AIPS1_REG_BASE + 0x44) #define AIPS1_OPACR10_11 (AIPS1_REG_BASE + 0x45) #define AIPS1_OPACR12_13 (AIPS1_REG_BASE + 0x46) #define AIPS1_OPACR14_15 (AIPS1_REG_BASE + 0x47) #define AIPS1_OPACR16_17 (AIPS1_REG_BASE + 0x48) #define AIPS1_OPACR18_19 (AIPS1_REG_BASE + 0x49) #define AIPS1_OPACR20_21 (AIPS1_REG_BASE + 0x4a) #define AIPS1_OPACR22_23 (AIPS1_REG_BASE + 0x4b) #define AIPS1_OPACR24_25 (AIPS1_REG_BASE + 0x4c) #define AIPS1_OPACR26_27 (AIPS1_REG_BASE + 0x4d) #define AIPS1_OPACR28_29 (AIPS1_REG_BASE + 0x4e) #define AIPS1_OPACR30_31 (AIPS1_REG_BASE + 0x4f) /* ----------------------------------------------------------------------------- */ /* INTC Registers */ /* ----------------------------------------------------------------------------- */ #define INTC0_IPRH (INTC0_BASE + 0x00) #define INTC0_IPRL (INTC0_BASE + 0x04) #define INTC0_IMRH (INTC0_BASE + 0x08) ⌨️ 快捷键说明
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