sdram_cache_test.c

来自「Freescale MCF5445evb 参考测试代码」· C语言 代码 · 共 101 行

    /* Initialize two regions of SDRAM with known data */
    for (i = 0; i < sizeof(test_data)/4; i++)
    {
        *(uint32*)(SDRAM_ADDRESS + i*4) = test_data[i];
        *(uint32*)(SDRAM_ADDRESS + 0x1000000 + i*4) = test_data[i];
    }
    
    /* Enable bursting */
    MCF_SCM_BCR = 0
        | MCF_SCM_BCR_GBW
        | MCF_SCM_BCR_GBR
        | 0x00000004;
     
    /* Setup CACR to enable data cache; default mode is inhibited-precise */
    mcf5xxx_wr_cacr(0
        | MCF5XXX_CACR_DEC
        | MCF5XXX_CACR_DDCM_IP
        | MCF5XXX_CACR_DCINVA);
        
    /* Use an acr to allow caching in a 16MB region of SDRAM 
     * Cached Addresses: SDRAM_ADDRESS to SDRAM_ADDRESS + 0xFFFFFF */
    mcf5xxx_wr_acr0(0
        | MCF5XXX_ACR_AB(SDRAM_ADDRESS)
        | MCF5XXX_ACR_AM_16M
        | MCF5XXX_ACR_EN
        | MCF5XXX_ACR_SM_IGNORE
        | MCF5XXX_ACR_DCM_CB);
           

    /* access at 0-aligned address to pull a line into cache */
    temp1 = *(uint32*)(SDRAM_ADDRESS + 0);
    temp2 = *(uint32*)(SDRAM_ADDRESS + 0x1000000 + 0);
    //ASSERT (temp1 == test_data[0]);
    //ASSERT (temp2 == test_data[0]);
    
    src1 = (uint32*)(SDRAM_ADDRESS);
    src2 = (uint32*)(SDRAM_ADDRESS + 0x1000000);
    printf("\n0x0 aligned access:\n");
    printf("\t\tnon-cached data\tcached data\n");
    printf("-----------------------------------------------\n");
    for (i = 0; i < 4; i++)
    {
        printf("Offset %02x:\t%08x\t%08x\n", i*4, src1[i], src2[i]);
        //ASSERT(src1[i] == test_data[i]);
        //ASSERT(src2[i] == test_data[i]);
    }
    
    /* access at 4-aligned address to pull a line into cache */
    temp1 = *(uint32*)(SDRAM_ADDRESS + 16 + 4);
    temp2 = *(uint32*)(SDRAM_ADDRESS + 0x1000000 + 16 + 4);
    //ASSERT (temp1 == test_data[1]);
    //ASSERT (temp2 == test_data[1]);
    
    src1 = (uint32*)(SDRAM_ADDRESS + 16);
    src2 = (uint32*)(SDRAM_ADDRESS + 0x1000000 + 16);
    printf("\n0x4 aligned access:\n");
    printf("\t\tnon-cached \tcached \n");
    printf("-----------------------------------------------\n");
    for (i = 0; i < 4; i++)
    {
        printf("Offset %02x:\t%08x\t%08x\n", i*4+16, src1[i], src2[i]);
        //ASSERT(src1[i] == test_data[i]);
        //ASSERT(src2[i] == test_data[i]);
    }
        
    /* access at 8-aligned address to pull a line into cache */
    temp1 = *(uint32*)(SDRAM_ADDRESS + 32 + 8);
    temp2 = *(uint32*)(SDRAM_ADDRESS + 0x1000000 + 32 + 8);
    //ASSERT (temp1 == test_data[2]);
    //ASSERT (temp2 == test_data[2]);
    
    src1 = (uint32*)(SDRAM_ADDRESS + 32);
    src2 = (uint32*)(SDRAM_ADDRESS + 0x1000000 + 32);
    printf("\n0x8 aligned access:\n");
    printf("\t\tnon-cached \tcached \n");
    printf("-----------------------------------------------\n");
    for (i = 0; i < 4; i++)
    {
        printf("Offset %02x:\t%08x\t%08x\n", i*4+32, src1[i], src2[i]);
        //ASSERT(src1[i] == test_data[i]);
        //ASSERT(src2[i] == test_data[i]);
    }
        
    /* access at C-aligned address to pull a line into cache */
    temp1 = *(uint32*)(SDRAM_ADDRESS + 48 + 0xC);
    temp2 = *(uint32*)(SDRAM_ADDRESS + 0x1000000 + 48 + 0xC);
    //ASSERT (temp1 == test_data[3]);
    //ASSERT (temp2 == test_data[3]);
    
    src1 = (uint32*)(SDRAM_ADDRESS + 48);
    src2 = (uint32*)(SDRAM_ADDRESS + 0x1000000 + 48);
    printf("\n0xC aligned access:\n");
    printf("\t\tnon-cached\tcached\n");
    printf("-----------------------------------------------\n");
    for (i = 0; i < 4; i++)
    {
        printf("Offset %02x:\t%08x\t%08x\n", i*4+48, src1[i], src2[i]);
        //ASSERT(src1[i] == test_data[i]);
        //ASSERT(src2[i] == test_data[i]);
    }