jamaica_tests.c

来自「Freescale MCF5445evb 参考测试代码」· C语言 代码 · 共 526 行

/*! 
 * \file    jamaica_tests.c
 * \brief   Jamaica hardware test routines
 * 
 * This file contains platform specific test routines.
 *
 * \author  Michael Norman
 * \version $Revision: 1.9 $
 */

#include "common.h"
#include "jamaica_tests.h"
#include "memtest.h"
#include "strata_flash.h"
#include "amd_flash.h"
#include "uart.h"
//#include "ata_tests.h"

__interrupt__
void irq1_handler (void);
__interrupt__
void irq3_handler (void);
__interrupt__
void irq4_handler (void);
__interrupt__
void irq7_handler (void);

int test_data[] = {
    0x00112233, 0x44556677, 0x8899AABB, 0xCCDDEEFF,
    0x00112233, 0x44556677, 0x8899AABB, 0xCCDDEEFF,
    0x00112233, 0x44556677, 0x8899AABB, 0xCCDDEEFF,
    0x00112233, 0x44556677, 0x8899AABB, 0xCCDDEEFF,
    0x00001111, 0x22223333, 0x44445555, 0x66667777,
    0x88889999, 0xAAAABBBB, 0xCCCCDDDD, 0xEEEEFFFF,
    0x00000000, 0x11111111, 0x22222222, 0x33333333,
    0x44444444, 0x55555555, 0x66666666, 0x77777777,
    0x11111111, 0x22222222, 0x44444444, 0x88888888,
    0xAAAAAAAA, 0x55555555, 0x99999999, 0x66666666,
    0xEEEEEEEE, 0x77777777, 0xFFFFFFFF, 0x00000000,
    0x33333333, 0xCCCCCCCC, 0xDEADBEEF, 0xFEEDFACE 
};

#define SPARE_SRAM  0x80006000

int 
mram_test (void);

/********************************************************************/
void 
main (void)
{
    int result = 0;
    uint32 test;

#if 0
    mcf5xxx_wr_cacr(0
        | MCF5XXX_CACR_BEC
        | MCF5XXX_CACR_BCINVA
        | MCF5XXX_CACR_IEC
        | MCF5XXX_CACR_ICINVA);
#endif
        
    //printf("\nPerforming Jamaica tests...\n");
    
    /* Enable interrupts in the Edge Port */
    MCF_EPORT_EPPAR = 0
        | MCF_EPORT_EPPAR_EPPA1_RISING
        | MCF_EPORT_EPPAR_EPPA3_RISING
        | MCF_EPORT_EPPAR_EPPA4_RISING
        | MCF_EPORT_EPPAR_EPPA7_RISING;
    MCF_EPORT_EPIER = 0
        | MCF_EPORT_EPIER_EPIE1
        | MCF_EPORT_EPIER_EPIE3
        | MCF_EPORT_EPIER_EPIE4
        | MCF_EPORT_EPIER_EPIE7;
         
    /* Enable interrupts in the interrupt controller */
    MCF_INTC0_CIMR = MCF_INTC0_ICR1 = 1;
    MCF_INTC0_CIMR = MCF_INTC0_ICR3 = 3;
    MCF_INTC0_CIMR = MCF_INTC0_ICR4 = 4;
    MCF_INTC0_CIMR = MCF_INTC0_ICR7 = 7;
    
    mcf5xxx_set_handler (64 + 1, (ADDRESS) irq1_handler);
    mcf5xxx_set_handler (64 + 3, (ADDRESS) irq3_handler);
    mcf5xxx_set_handler (64 + 4, (ADDRESS) irq4_handler);
    mcf5xxx_set_handler (64 + 7, (ADDRESS) irq7_handler);

    /* Enable interrupts in the core */
    mcf5xxx_irq_enable();

    platform_led_display(0xFF);

    //sdram_cache_test();
    
    platform_led_display(0x1);
    result |= ulpi_test();
    platform_led_display(0x2);
    result |= serial_flash_test();
    platform_led_display(0x3);
    result |= sdram_test();
    platform_led_display(0x4);
    result |= flash0_test();
    platform_led_display(0x5);
    result |= flash1_test();
    platform_led_display(0x6);
    result |= uart0_test();
    platform_led_display(0x7);
    result |= uart1_test();
    platform_led_display(0x8);
    //result |= audio_test();
    platform_led_display(0x9);
    result |= eth_test(0);
    platform_led_display(0x10);
    result |= eth_test(1);
    
#ifdef DEBUG_PRINT
    if (result & FLASH0_FAIL)
        printf("Flash0 failed\n");
    if (result & SDRAM_FAIL)
        printf("SDRAM failed\n");
    if (result & ETH0_FAIL_FEC_LOOP)
        printf("Eth0 failed FEC loop\n");
    if (result & ETH0_FAIL_PHY_LOOP)
        printf("Eth0 failed PHY loop\n");
    if (result & ETH0_FAIL_CBL_LOOP)
        printf("Eth0 failed CBL loop\n");
    if (result & ETH1_FAIL_FEC_LOOP)
        printf("Eth1 failed FEC loop\n");
    if (result & ETH1_FAIL_PHY_LOOP)
        printf("Eth1 failed PHY loop\n");
    if (result & ETH1_FAIL_CBL_LOOP)
        printf("Eth1 failed CBL loop\n");
    if (result & SPIFLASH_FAIL)
        printf("Serial Flash failed\n");
    if (result & UART0_FAIL)
        printf("UART0 Failed\n");
    if (result & UART1_FAIL)
        printf("UART1 Failed\n");
    printf("All tests complete\n");    
#endif
    if (result)
    {
        FPGA_7SEGMENT = 0xFA;
        ASSERT(FALSE);
    }
    else
    {
        FPGA_LEDS = 0x3;
        FPGA_7SEGMENT = 0x00;
        CPLD_LEDS = 0xFF;
    }
    
    while(1) {
/*
        mram_test();
        
        FPGA_LEDS = 0x0;
        FPGA_LEDS = 0x3;
        nop();
        FPGA_LEDS = 0x3;
        FPGA_LEDS = 0x0;
        nop();
        FPGA_7SEGMENT = 0x00;
        FPGA_7SEGMENT = 0xFF;
        nop();
        FPGA_7SEGMENT = 0xFF;
        FPGA_7SEGMENT = 0x00;
        nop();
        CPLD_LEDS = 0xFF;
        CPLD_LEDS = 0x00;
        nop();
        CPLD_LEDS = 0x00;
        CPLD_LEDS = 0xFF;
        nop();
*/
    };
}
/********************************************************************/
int 
mram_test (void)
{
    int i;
    uint16 data;
    vuint16 *mram = (vuint16 *)MRAM_ADDRESS;
    uint16 *mram_test_data = (uint16 *)test_data;
    uint16 read_data[40];
    
#if 0
    MCF_FBCS_CSCR3 = 0
        | MCF_FBCS_CSCR_AA          /* Auto acknowledge */
        | MCF_FBCS_CSCR_WS(8)       /* Wait states */
        | MCF_FBCS_CSCR_BEM         /* Byte-enable mode */
        | MCF_FBCS_CSCR_PS_16;      /* Port size: 16 bits */
#endif

    i = 0;
    mram[i] = 0x0000;
    data = mram[i];
    
    mram[i+1] = 0x1111;
    data = mram[i+1];
    
    mram[i+2] = 0x2222;
    data = mram[i+2];
    
    mram[i+3] = 0x3333;
    data = mram[i+3];
    
    mram[i+4] = 0x4444;
    data = mram[i+4];
    
    
    /* Clear the contents of MRAM */
    for (i = 0; i < 40; i++)
        mram[i] = 0x0000;
    
    /* Verify the contents */
    for (i = 0; i < 40; i++)
    {
        //read_data[i] = mram[i];
    //}
    //for (i = 0; i < 40; i++)
    //{
        if (!(i % 4))
            printf("\n0x%04x:  ", &mram[i]);
        printf("%04x ", mram[i]);//read_data[i]);
        //ASSERT(read_data[i] == 0x0000);
    }
    
    /* Write test data */
    for (i = 0; i < sizeof(test_data); i++)
        mram[i] = mram_test_data[i];
    
    /* Verify the contents */
    for (i = 0; i < 40; i++)
    {
        if (!(i % 4))
            printf("\n0x%04x:  ", &mram[i]);
        printf("%04x ", mram[i]);
        //ASSERT(mram[i] == mram_test_data[i]);
    }

}
/********************************************************************/
void
burst_writes(int dest, int lines)
{
    int i, j;
    
    for (i = 0; i < lines; i+=16)
        mcf5xxx_move_line((ADDRESS)&test_data[0], dest + i);
}
/********************************************************************/
int 
sdram_test (void)
{
	uint32 mem1, mem2, data1, data2;
	int i, fail;

    if (memtest_databus_32((uint32 *)SDRAM_ADDRESS)                   ||
        memtest_databus_32((uint32 *)SDRAM_ADDRESS+1)                 ||
        memtest_databus_32((uint32 *)SDRAM_ADDRESS+2)                 ||
        memtest_databus_32((uint32 *)SDRAM_ADDRESS+3)                 ||
        memtest_databus_32((uint32 *)(SDRAM_ADDRESS+SDRAM_SIZE/2))    ||
        memtest_databus_32((uint32 *)(SDRAM_ADDRESS+SDRAM_SIZE/2)+1)  ||
        memtest_databus_32((uint32 *)(SDRAM_ADDRESS+SDRAM_SIZE/2)+2)  ||
        memtest_databus_32((uint32 *)(SDRAM_ADDRESS+SDRAM_SIZE/2)+3))
        return SDRAM_FAIL;
    
    if (memtest_addrbus_32((uint32 *) (SDRAM_ADDRESS+(SDRAM_SIZE/8*3)), 
                          SDRAM_SIZE/4))
        return SDRAM_FAIL;
        
    if (memtest_device_32((uint32 *) (SDRAM_ADDRESS+(SDRAM_SIZE/16*7)), 
                          SDRAM_SIZE/8))
        return SDRAM_FAIL;

#if 0
    /* Disable bursting on XBS */
    MCF_SCM_BCR = 0;
    
    /* Clear a small portion of SDRAM */
    for (i = 0; i < sizeof(test_data); i+=4)
        *(uint32*)(SDRAM_ADDRESS + i) = 0;
        

    
    /* Move lines of test data into the SDRAM (with bursting disabled) */
    mcf5xxx_move_line((ADDRESS)&test_data[0], SDRAM_ADDRESS + 0);
    mcf5xxx_move_line((ADDRESS)&test_data[4], SDRAM_ADDRESS + 16);
    mcf5xxx_move_line((ADDRESS)&test_data[8], SDRAM_ADDRESS + 32);
    mcf5xxx_move_line((ADDRESS)&test_data[12], SDRAM_ADDRESS + 48);
    mcf5xxx_move_line((ADDRESS)&test_data[16], SDRAM_ADDRESS + 64);
    

    printf("SDRAM contents after line moves with bursting disabled:");
    for (i = 0; i < sizeof(test_data); i+=2)
    {
        if (!(i % 16))
            printf("\n0x%08x:  ", (SDRAM_ADDRESS + i));
        printf("%04x ", *(uint16 *)(SDRAM_ADDRESS + i));
    }
    printf("\n\n");
#endif
#if 1
     
    /* Clear a small portion of SDRAM */
    for (i = 0; i < sizeof(test_data); i+=4)
        *(uint32*)(SDRAM_ADDRESS + i) = 0;
    
    /* burst from SRAM to SRAM */
    /*
    mcf5xxx_move_line((ADDRESS)&test_data[0], SPARE_SRAM + 0);
    mcf5xxx_move_line((ADDRESS)&test_data[4], SPARE_SRAM + 16);
    mcf5xxx_move_line((ADDRESS)&test_data[8], SPARE_SRAM + 32);
    mcf5xxx_move_line((ADDRESS)&test_data[12], SPARE_SRAM + 48);
    mcf5xxx_move_line((ADDRESS)&test_data[16], SPARE_SRAM + 64);
    */
    /* burst from SRAM to SDRAM */
    mcf5xxx_move_line((ADDRESS)&test_data[0], SDRAM_ADDRESS + 0);
    mcf5xxx_move_line((ADDRESS)&test_data[4], SDRAM_ADDRESS + 16);
    mcf5xxx_move_line((ADDRESS)&test_data[8], SDRAM_ADDRESS + 32);
    mcf5xxx_move_line((ADDRESS)&test_data[12], SDRAM_ADDRESS + 48);
    mcf5xxx_move_line((ADDRESS)&test_data[16], SDRAM_ADDRESS + 64);

    /* burst from SDRAM to SRAM */
    /*
    mcf5xxx_move_line((ADDRESS)(SDRAM_ADDRESS + 0), SPARE_SRAM + 0);
    mcf5xxx_move_line((ADDRESS)(SDRAM_ADDRESS + 16), SPARE_SRAM + 16);
    mcf5xxx_move_line((ADDRESS)(SDRAM_ADDRESS + 32), SPARE_SRAM + 32);
    mcf5xxx_move_line((ADDRESS)(SDRAM_ADDRESS + 48), SPARE_SRAM + 48);
    mcf5xxx_move_line((ADDRESS)(SDRAM_ADDRESS + 64), SPARE_SRAM + 64);
    */
    /*
    printf("SDRAM contents after line moves with bursting enabled:");
    for (i = 0; i < sizeof(test_data); i+=2)
    {
        if (!(i % 16))
            printf("\n0x%08x:  ", (SDRAM_ADDRESS + i));
        printf("%04x ", *(uint16 *)(SDRAM_ADDRESS + i));
    }
    printf("\n");
    */
    for (i = 0; i < 80/4; i++)
    {
        if (test_data[i] != *(uint32 *)(SDRAM_ADDRESS + i*4))
            return SDRAM_FAIL;
    }
    
#endif    
#if 0
    /* Page tests */
	for (i = 0; i < SDRAM_SIZE; i+=4)
		*(uint32 *) (SDRAM_ADDRESS + i) = SDRAM_ADDRESS + i;
	
	for (mem1 = SDRAM_ADDRESS; 
     	 mem1 < (SDRAM_ADDRESS + SDRAM_SIZE); 
     	 mem1+=SDRAM_SIZE/4)
	{
	    for(mem2 = SDRAM_ADDRESS; mem2 < SDRAM_ADDRESS + SDRAM_SIZE; mem2 += 0x400)
		{ 
			data1 = *(uint32 *)(mem1);
			data2 = *(uint32 *)(mem2);
	
			if (data1 != mem1)
                return SDRAM_FAIL;
			if (data2 != mem2)
                return SDRAM_FAIL;
		}
	}
#endif
    return SDRAM_PASS;
}
/********************************************************************/
void
sdram_cache_test (void)
{
    int i;
    uint32 temp, *src;
    
    printf("SDRAM/Cache Test\n");
    
    src = (uint32*)(SDRAM_ADDRESS);

    /* Initialize SDRAM with known data */
    for (i = 0; i < sizeof(test_data)/4; i++)
    {
        src[i] = test_data[i];
    }
    
    /* Enable bursting in XBS */
    MCF_SCM_BCR = 0
        | MCF_SCM_BCR_GBW
        | MCF_SCM_BCR_GBR
        | 0x00000004;
     
    /* Setup CACR to enable data cache; default mode is inhibited-precise */
    mcf5xxx_wr_cacr(0
        | MCF5XXX_CACR_DEC
        | MCF5XXX_CACR_DDCM_IP
        | MCF5XXX_CACR_DCINVA);
        
    /* First 16MB of SDRAM will be copy-back cacheable */ 
    mcf5xxx_wr_acr0(0
        | MCF5XXX_ACR_AB(SDRAM_ADDRESS)
        | MCF5XXX_ACR_AM_16M
        | MCF5XXX_ACR_EN
        | MCF5XXX_ACR_SM_IGNORE
        | MCF5XXX_ACR_CM_CB);
        
    /*****************************
     * Access at 0x0 aligned address
     */
    temp = *(uint32*)(SDRAM_ADDRESS + 0);
    
    printf("\n0x0 aligned: ");
    for (i = 0; i < 4; i++)
    {
        printf(" %08x", src[i]);
    }
    
    /* Invalidate the data cache */
    mcf5xxx_wr_cacr(0
        | MCF5XXX_CACR_DEC
        | MCF5XXX_CACR_DDCM_IP
        | MCF5XXX_CACR_DCINVA);

    /*****************************
     * Access at 0x4 aligned address
     */
    temp = *(uint32*)(SDRAM_ADDRESS + 4);
    
    printf("\n0x4 aligned: ");
    for (i = 0; i < 4; i++)
    {
        printf(" %08x", src[i]);
    }
    
    /* Invalidate the data cache */
    mcf5xxx_wr_cacr(0
        | MCF5XXX_CACR_DEC
        | MCF5XXX_CACR_DDCM_IP
        | MCF5XXX_CACR_DCINVA);

    /*****************************
     * Access at 0x8 aligned address
     */
    temp = *(uint32*)(SDRAM_ADDRESS + 8);
    
    printf("\n0x8 aligned: ");
    for (i = 0; i < 4; i++)
    {
        printf(" %08x", src[i]);
    }
    
    /* Invalidate the data cache */
    mcf5xxx_wr_cacr(0
        | MCF5XXX_CACR_DEC
        | MCF5XXX_CACR_DDCM_IP
        | MCF5XXX_CACR_DCINVA);

    /*****************************
     * Access at 0xC aligned address
     */
    temp = *(uint32*)(SDRAM_ADDRESS + 12);
    
    printf("\n0xC aligned: ");
    for (i = 0; i < 4; i++)
    {
        printf(" %08x", src[i]);
    }
    printf("\n");
    
    /* Disable and invalidate the data cache */
    mcf5xxx_wr_cacr(MCF5XXX_CACR_DCINVA);       
}
/********************************************************************/
/*!
 * \brief   Interrupt handler for IRQ7
 */
__interrupt__
void irq7_handler (void)
{
    printf("IRQ7\n");

    /* Clear the interrupt event */
    MCF_EPORT_EPFR = MCF_EPORT_EPFR_EPF7;
}
/********************************************************************/
/*!
 * \brief   Interrupt handler for IRQ4
 */
__interrupt__
void irq4_handler (void)
{
    printf("IRQ4\n");

    /* Clear the interrupt event */
    MCF_EPORT_EPFR = MCF_EPORT_EPFR_EPF4;
}
/********************************************************************/
/*!
 * \brief   Interrupt handler for IRQ3
 */
__interrupt__
void irq3_handler (void)
{
    printf("IRQ3\n");

    /* Clear the interrupt event */
    MCF_EPORT_EPFR = MCF_EPORT_EPFR_EPF3;
}
/********************************************************************/
/*!
 * \brief   Interrupt handler for IRQ1
 */
__interrupt__
void irq1_handler (void)
{
    printf("IRQ1\n");

    /* Clear the interrupt event */
    MCF_EPORT_EPFR = MCF_EPORT_EPFR_EPF1;
}
/********************************************************************/