flexbus_tests.c

Freescale MCF5445evb 参考测试代码

/*!
 * \file    flexbus_tests.c
 * \brief   Flexbus Test Routines
 *
 * Test the Flexbus interface on Jamaica
 *
 * \version $Revision: 1.1 $
 * \author  Michael Norman
 */

#include "common.h"
#include "clock.h"
#include "flexbus_tests.h"
#include "memtest.h"

/********************************************************************/

/*! Initialized data for test purposes */
int test_data[] = {
    0x00112233, 0x44556677, 0x8899AABB, 0xCCDDEEFF,
    0x00112233, 0x44556677, 0x8899AABB, 0xCCDDEEFF,
    0x00112233, 0x44556677, 0x8899AABB, 0xCCDDEEFF,
    0x00112233, 0x44556677, 0x8899AABB, 0xCCDDEEFF,
    0x00001111, 0x22223333, 0x44445555, 0x66667777,
    0x88889999, 0xAAAABBBB, 0xCCCCDDDD, 0xEEEEFFFF,
    0x00000000, 0x11111111, 0x22222222, 0x33333333,
    0x44444444, 0x55555555, 0x66666666, 0x77777777,
    0x11111111, 0x22222222, 0x44444444, 0x88888888,
    0xAAAAAAAA, 0x55555555, 0x99999999, 0x66666666,
    0xEEEEEEEE, 0x77777777, 0xFFFFFFFF, 0x00000000,
    0x33333333, 0xCCCCCCCC, 0xDEADBEEF, 0xFEEDFACE 
};

/********************************************************************/
/*!
 * \brief   Flexbus Register Dump 
 * \param   none
 * \return  none
 */
void
flexbus_register_dump (void)
{
    printf("FBCS Registers:\n");
    printf("CSAR0        = %08X\n", MCF_FBCS_CSAR0);
    printf("CSMR0        = %08X\n", MCF_FBCS_CSMR0);
    printf("CSCR0        = %08X\n", MCF_FBCS_CSCR0);
    printf("CSAR1        = %08X\n", MCF_FBCS_CSAR1);
    printf("CSMR1        = %08X\n", MCF_FBCS_CSMR1);
    printf("CSCR1        = %08X\n", MCF_FBCS_CSCR1);
    printf("CSAR2        = %08X\n", MCF_FBCS_CSAR2);
    printf("CSMR2        = %08X\n", MCF_FBCS_CSMR2);
    printf("CSCR2        = %08X\n", MCF_FBCS_CSCR2);
    printf("CSAR3        = %08X\n", MCF_FBCS_CSAR3);
    printf("CSMR3        = %08X\n", MCF_FBCS_CSMR3);
    printf("CSCR3        = %08X\n", MCF_FBCS_CSCR3);
}

/********************************************************************/
/*!
 * \brief   Flexbus Burst Read Test
 * \param   addr Flexbus test address 
 * \return  0 for success, non-zero for failure
 *
 * Test aligned and mis-aligned burst reads from the Flexbus controller. 
 * This test uses the cache to generate the bursts.
 */
int
flexbus_burst_read (ADDRESS addr)
{
    int i;
    uint32 lw0, lw1, lw2, lw3, *src;

    #ifdef FLEXBUS_DEBUG_PRINT
        printf("Flexbus Burst Read Test:\n");
    #endif

    /* Initialize Flexbus with known data */
    src = (uint32*)(addr);
    for (i = 0; i < sizeof(test_data)/4; i++)
        src[i] = test_data[i];
    
    /* Setup CACR to enable data cache; default mode is inhibited-precise */
    cpu_dcache_enable(0x00000000, SIZE_1G, MCF5XXX_ACR_CM_CB);
        
    /* Access at 0x0 aligned address */
    lw0 = *(uint32*)(addr + 0);
    lw1 = *(uint32*)(addr + 4);
    lw2 = *(uint32*)(addr + 8);
    lw3 = *(uint32*)(addr + 12);
    
    if ((lw0 != test_data[0]) ||
        (lw1 != test_data[1]) ||
        (lw2 != test_data[2]) ||
        (lw3 != test_data[3]))
        return 1;
        
    #ifdef FLEXBUS_DEBUG_PRINT
        printf("\n0x0 aligned: ");
        for (i = 0; i < 4; i++)
        {
            printf(" %08x", src[i]);
        }
    #endif
    
    /* Invalidate the data cache */
    mcf5xxx_wr_cacr(0
        | MCF5XXX_CACR_DEC
        | MCF5XXX_CACR_DDCM_IP
        | MCF5XXX_CACR_DCINVA);

    /* Access at 0x4 aligned address */
    lw1 = *(uint32*)(addr + 4);
    lw2 = *(uint32*)(addr + 8);
    lw3 = *(uint32*)(addr + 12);
    lw0 = *(uint32*)(addr + 0);
   
    if ((lw0 != test_data[0]) ||
        (lw1 != test_data[1]) ||
        (lw2 != test_data[2]) ||
        (lw3 != test_data[3]))
        return 1;

    #ifdef FLEXBUS_DEBUG_PRINT
        printf("\n0x4 aligned: ");
        for (i = 0; i < 4; i++)
        {
            printf(" %08x", src[i]);
        }
    #endif
    
    /* Invalidate the data cache */
    mcf5xxx_wr_cacr(0
        | MCF5XXX_CACR_DEC
        | MCF5XXX_CACR_DDCM_IP
        | MCF5XXX_CACR_DCINVA);

    /* Access at 0x8 aligned address */
    lw2 = *(uint32*)(addr + 8);
    lw3 = *(uint32*)(addr + 12);
    lw0 = *(uint32*)(addr + 0);
    lw1 = *(uint32*)(addr + 4);
   
    if ((lw0 != test_data[0]) ||
        (lw1 != test_data[1]) ||
        (lw2 != test_data[2]) ||
        (lw3 != test_data[3]))
        return 1;

    #ifdef FLEXBUS_DEBUG_PRINT
        printf("\n0x8 aligned: ");
        for (i = 0; i < 4; i++)
        {
            printf(" %08x", src[i]);
        }
    #endif
    
    /* Invalidate the data cache */
    mcf5xxx_wr_cacr(0
        | MCF5XXX_CACR_DEC
        | MCF5XXX_CACR_DDCM_IP
        | MCF5XXX_CACR_DCINVA);

    /* Access at 0x4 aligned address */
    lw1 = *(uint32*)(addr + 4);
    lw2 = *(uint32*)(addr + 8);
    lw3 = *(uint32*)(addr + 12);
    lw0 = *(uint32*)(addr + 0);
   
    if ((lw0 != test_data[0]) ||
        (lw1 != test_data[1]) ||
        (lw2 != test_data[2]) ||
        (lw3 != test_data[3]))
        return 1;

    #ifdef FLEXBUS_DEBUG_PRINT
        printf("\n0x4 aligned: ");
        for (i = 0; i < 4; i++)
        {
            printf(" %08x", src[i]);
        }
        printf("\n");
    #endif
    
    /* Disable and invalidate the data cache */
    mcf5xxx_wr_cacr(MCF5XXX_CACR_DCINVA);
    
    return 0;
}
/********************************************************************/
/*!
 * \brief   Flexbus Burst Write Test
 * \param   addr Flexbus test address 
 * \return  0 for pass, non-zero for failure
 *
 * Test aligned bursts to the Flexbus controller.  This test uses the
 * movem instruction of the ColdFire core to burst to the memory.
 *
 * \warning This test does not perform mis-aligned burst writes. There
 *          is no bus master on the MCF5445x that is capable of bursting
 *          to the Flexbus on a non-line-aligned address.
 */
int
flexbus_burst_write (ADDRESS addr)
{
    int i;
    uint32 lw0, lw1, lw2, lw3, *dest;

    #ifdef FLEXBUS_DEBUG_PRINT
        printf("Flexbus Burst Write Test:\n");
    #endif

    /* Initialize Flexbus with known data */
    dest = (uint32*)(addr);
    for (i = 0; i < sizeof(test_data)/4; i++)
        dest[i] = 0x0;
        
    /* Burst writes */
    for (i = 0; i < sizeof(test_data); i+=16)
    {
        mcf5xxx_move_line((ADDRESS)&test_data[i/4], (ADDRESS)&dest[i/4]);
    }

    /* Verify data in Flexbus */
    for (i = 0; i < sizeof(test_data)/4; i++)
    {
        if (dest[i] != test_data[i])
            return 1;
    }
    
    return 0;
}
/********************************************************************/
/*!
 * \brief   Flexbus Data Bus Test
 * \param   addr Flexbus test address 
 * \return  0 for success, non-zero for failure
 */
int
flexbus_data_test(ADDRESS address)
{
    return (memtest_databus_8((uint8*)address) || 
            memtest_databus_16((uint16*)address) || 
            memtest_databus_16((uint16*)address+1) ||
            memtest_databus_32((uint32*)address) ||
            memtest_databus_32((uint32*)address+1) ||
            memtest_databus_32((uint32*)address+2) ||
            memtest_databus_32((uint32*)address+3));
}
/********************************************************************/
/*!
 * \brief   Flexbus Address Bus Test
 * \param   addr    Flexbus test address 
 * \param   bytes   Number of bytes to test
 * \return  0 for success, non-zero for failure
 */
int
flexbus_addr_test(ADDRESS address, int bytes)
{
    return (memtest_addrbus_8((uint8*)address, bytes) ||
            memtest_addrbus_16((uint16*)address, bytes) ||
            memtest_addrbus_16((uint16*)address+1, bytes) ||
            memtest_addrbus_32((uint32*)address, bytes) ||
            memtest_addrbus_32((uint32*)address+1, bytes) ||
            memtest_addrbus_32((uint32*)address+2, bytes) ||
            memtest_addrbus_32((uint32*)address+3, bytes));
}
/********************************************************************/
/*!
 * \brief   Flexbus Device Test
 * \param   addr Flexbus test address 
 * \param   bytes   Number of bytes to test
 * \return  0 for success, non-zero for failure
 */
int
flexbus_device_test(ADDRESS address, int bytes)
{
    return (memtest_device_8((uint8*)address, bytes) ||
            memtest_device_16((uint16*)address, bytes) ||
            memtest_device_32((uint32*)address, bytes));
}
/********************************************************************/
/*!
 * \brief   Flexbus Invalid Access Test
 *          Access a region within the Flexbus slave port, but outside
 *          the valid Flexbus mask range
 */
void
flexbus_invalid_access(void)
{
    vuint32 data;
    
    #ifdef DEBUG_PRINT
    printf("\nPerforming invalid access tests.\n");
    printf("You should see two internal bus faults next...\n");
    #endif
    printf("\nNot implemented yet.\n");
    
    //data = *(vuint32 *)(Flexbus_ADDRESS + Flexbus_SIZE);
    //*(vuint32 *)(Flexbus_ADDRESS + Flexbus_SIZE) = data;    
}
/********************************************************************/
/*!
 * \brief   Flexbus Jitter Test
 */
void
flexbus_jitter(int max)
{
    int pll_flags, i;
    uint8 max_data[16] = {0xFF, 0x00, 0xFF, 0x00, 0xFF, 0x00, 0xFF, 0x00, 
                          0xFF, 0x00, 0xFF, 0x00, 0xFF, 0x00, 0xFF, 0x00};
    uint8 min_data[16];
                        
    memset(min_data, 0, sizeof(min_data));
    
    /* Initialize the on-chip system PLL -- max FBCLK */
    clock_pll_init(FREF, FSYS, 0, NULL);
    
    /* Setup FPGA chip select for fastest operation */
    MCF_FBCS_CSAR3 = MCF_FBCS_CSAR_BA(FPGA_ADDRESS);
    MCF_FBCS_CSCR3 = 0
        | MCF_FBCS_CSCR_BSTW        /* Burst Writes */
        | MCF_FBCS_CSCR_AA          /* Auto acknowledge */
        | MCF_FBCS_CSCR_WS(0)       /* Wait states */
        | MCF_FBCS_CSCR_PS_8;      /* Port size: 32 bits */
    MCF_FBCS_CSMR3 = 0
        | MCF_FBCS_CSMR_BAM((FPGA_SIZE-1)>>16)
        | MCF_FBCS_CSMR_V;          /* Activate this chip-select */
        
    /* Enable instruction cache */
    cpu_icache_enable(0, SIZE_2G);
    
    if (FALSE == max)
    {
        /* min jitter / baseline */
        while (!char_present())
        {
            for (i = 0; i < 100000; i++)
                nop();
        }
    }
    else
    {
        /* max jitter */
        while (!char_present())
        {
            for (i = 0; i < 100000; i++)
                nop();
            /*
            mcf5xxx_move_line((ADDRESS)min_data, (ADDRESS)FPGA_ADDRESS);
            mcf5xxx_move_line((ADDRESS)min_data, (ADDRESS)FPGA_ADDRESS);
            mcf5xxx_move_line((ADDRESS)min_data, (ADDRESS)FPGA_ADDRESS);
            mcf5xxx_move_line((ADDRESS)min_data, (ADDRESS)FPGA_ADDRESS);
            mcf5xxx_move_line((ADDRESS)min_data, (ADDRESS)FPGA_ADDRESS);
            mcf5xxx_move_line((ADDRESS)min_data, (ADDRESS)FPGA_ADDRESS);
            mcf5xxx_move_line((ADDRESS)min_data, (ADDRESS)FPGA_ADDRESS);
            mcf5xxx_move_line((ADDRESS)min_data, (ADDRESS)FPGA_ADDRESS);
            */
            mcf5xxx_move_line((ADDRESS)max_data, (ADDRESS)FPGA_ADDRESS);
            mcf5xxx_move_line((ADDRESS)max_data, (ADDRESS)FPGA_ADDRESS);
            mcf5xxx_move_line((ADDRESS)max_data, (ADDRESS)FPGA_ADDRESS);
            mcf5xxx_move_line((ADDRESS)max_data, (ADDRESS)FPGA_ADDRESS);
            mcf5xxx_move_line((ADDRESS)max_data, (ADDRESS)FPGA_ADDRESS);
            mcf5xxx_move_line((ADDRESS)max_data, (ADDRESS)FPGA_ADDRESS);
            mcf5xxx_move_line((ADDRESS)max_data, (ADDRESS)FPGA_ADDRESS);
            mcf5xxx_move_line((ADDRESS)max_data, (ADDRESS)FPGA_ADDRESS);
        }
    }
    in_char();
}
/********************************************************************/
/*!
 * \brief   Perform all Flexbus tests
 * \return  0 for success, non-zero for failure
 */
int
flexbus_all_tests (void)
{
    int result = 0;
#if 0
    ADDRESS addr = (ADDRESS) Flexbus_ADDRESS;
    
    flexbus_invalid_access();
    
    if (flexbus_data_test(addr))
    {
        #ifdef DEBUG_PRINT
        printf("FAILED: flexbus_data_test()\n");
        #endif
        result += 1;
    }
    if (flexbus_addr_test(addr+(Flexbus_SIZE/8*3), Flexbus_SIZE/4))
    {
        #ifdef DEBUG_PRINT
        printf("FAILED: flexbus_addr_test()\n");
        #endif
        result += 1;
    }
    if (flexbus_device_test(addr+(Flexbus_SIZE/16*7), Flexbus_SIZE/8))
    {
        #ifdef DEBUG_PRINT
        printf("FAILED: flexbus_device_test()");
        #endif
        result += 1;
    }
    if (flexbus_burst_write(addr))
    {
        #ifdef DEBUG_PRINT
        printf("FAILED: flexbus_burst_write()\n");
        #endif
        result += 1;
    }
    if (flexbus_burst_read(addr))
    {
        #ifdef DEBUG_PRINT
        printf("FAILED: flexbus_burst_read()\n");
        #endif
        result += 1;
    }
    
    #ifdef DEBUG_PRINT
    if (result == 0)    
        printf("All Flexbus tests passed.\n");
    #endif 
    
#endif    
    return result;
}
/********************************************************************/