sram_tests.c

Freescale MCF5445evb 参考测试代码

/*!
 * \file    sram_tests.c
 * \brief   SRAM Test Routines
 *
 * Test the SRAM interface on Jamaica
 *
 * \version $Revision: 1.1 $
 * \author  Michael Norman
 */

#include "common.h"
#include "sram_tests.h"
#include "memtest.h"

/********************************************************************/

/*! Initialized data for test purposes */
int test_data[] = {
    0x00112233, 0x44556677, 0x8899AABB, 0xCCDDEEFF,
    0x00112233, 0x44556677, 0x8899AABB, 0xCCDDEEFF,
    0x00112233, 0x44556677, 0x8899AABB, 0xCCDDEEFF,
    0x00112233, 0x44556677, 0x8899AABB, 0xCCDDEEFF,
    0x00001111, 0x22223333, 0x44445555, 0x66667777,
    0x88889999, 0xAAAABBBB, 0xCCCCDDDD, 0xEEEEFFFF,
    0x00000000, 0x11111111, 0x22222222, 0x33333333,
    0x44444444, 0x55555555, 0x66666666, 0x77777777,
    0x11111111, 0x22222222, 0x44444444, 0x88888888,
    0xAAAAAAAA, 0x55555555, 0x99999999, 0x66666666,
    0xEEEEEEEE, 0x77777777, 0xFFFFFFFF, 0x00000000,
    0x33333333, 0xCCCCCCCC, 0xDEADBEEF, 0xFEEDFACE 
};

/********************************************************************/
/*!
 * \brief   SRAM Burst Read Test
 * \param   addr SRAM test address 
 * \return  0 for success, non-zero for failure
 *
 * Test aligned and mis-aligned burst reads from the SRAM controller. 
 * This test uses the cache to generate the bursts.
 */
int
sram_burst_read (ADDRESS addr)
{
    int i;
    uint32 lw0, lw1, lw2, lw3, *src;

    #ifdef SRAM_DEBUG_PRINT
        printf("SRAM Burst Read Test:\n");
    #endif

    /* Initialize SRAM with known data */
    src = (uint32*)(addr);
    for (i = 0; i < sizeof(test_data)/4; i++)
        src[i] = test_data[i];
    
    /* Setup CACR to enable data cache; default mode is inhibited-precise */
    mcf5xxx_wr_cacr(0
        | MCF5XXX_CACR_DEC
        | MCF5XXX_CACR_DDCM_IP
        | MCF5XXX_CACR_DCINVA);
        
    /* SRAM will be copy-back cacheable */ 
    mcf5xxx_wr_acr0(0
        | MCF5XXX_ACR_AB(SRAM_ADDRESS)
        | MCF5XXX_ACR_AM_256M
        | MCF5XXX_ACR_EN
        | MCF5XXX_ACR_SM_IGNORE
        | MCF5XXX_ACR_DCM_CB);
        
    /* Access at 0x0 aligned address */
    lw0 = *(uint32*)(addr + 0);
    lw1 = *(uint32*)(addr + 4);
    lw2 = *(uint32*)(addr + 8);
    lw3 = *(uint32*)(addr + 12);
    
    if ((lw0 != test_data[0]) ||
        (lw1 != test_data[1]) ||
        (lw2 != test_data[2]) ||
        (lw3 != test_data[3]))
        return 1;
        
    #ifdef SRAM_DEBUG_PRINT
        printf("\n0x0 aligned: ");
        for (i = 0; i < 4; i++)
        {
            printf(" %08x", src[i]);
        }
    #endif
    
    /* Invalidate the data cache */
    mcf5xxx_wr_cacr(0
        | MCF5XXX_CACR_DEC
        | MCF5XXX_CACR_DDCM_IP
        | MCF5XXX_CACR_DCINVA);

    /* Access at 0x4 aligned address */
    lw1 = *(uint32*)(addr + 4);
    lw2 = *(uint32*)(addr + 8);
    lw3 = *(uint32*)(addr + 12);
    lw0 = *(uint32*)(addr + 0);
   
    if ((lw0 != test_data[0]) ||
        (lw1 != test_data[1]) ||
        (lw2 != test_data[2]) ||
        (lw3 != test_data[3]))
        return 1;

    #ifdef SRAM_DEBUG_PRINT
        printf("\n0x4 aligned: ");
        for (i = 0; i < 4; i++)
        {
            printf(" %08x", src[i]);
        }
    #endif
    
    /* Invalidate the data cache */
    mcf5xxx_wr_cacr(0
        | MCF5XXX_CACR_DEC
        | MCF5XXX_CACR_DDCM_IP
        | MCF5XXX_CACR_DCINVA);

    /* Access at 0x8 aligned address */
    lw2 = *(uint32*)(addr + 8);
    lw3 = *(uint32*)(addr + 12);
    lw0 = *(uint32*)(addr + 0);
    lw1 = *(uint32*)(addr + 4);
   
    if ((lw0 != test_data[0]) ||
        (lw1 != test_data[1]) ||
        (lw2 != test_data[2]) ||
        (lw3 != test_data[3]))
        return 1;

    #ifdef SRAM_DEBUG_PRINT
        printf("\n0x8 aligned: ");
        for (i = 0; i < 4; i++)
        {
            printf(" %08x", src[i]);
        }
    #endif
    
    /* Invalidate the data cache */
    mcf5xxx_wr_cacr(0
        | MCF5XXX_CACR_DEC
        | MCF5XXX_CACR_DDCM_IP
        | MCF5XXX_CACR_DCINVA);

    /* Access at 0x4 aligned address */
    lw1 = *(uint32*)(addr + 4);
    lw2 = *(uint32*)(addr + 8);
    lw3 = *(uint32*)(addr + 12);
    lw0 = *(uint32*)(addr + 0);
   
    if ((lw0 != test_data[0]) ||
        (lw1 != test_data[1]) ||
        (lw2 != test_data[2]) ||
        (lw3 != test_data[3]))
        return 1;

    #ifdef SRAM_DEBUG_PRINT
        printf("\n0x4 aligned: ");
        for (i = 0; i < 4; i++)
        {
            printf(" %08x", src[i]);
        }
        printf("\n");
    #endif
    
    /* Disable and invalidate the data cache */
    mcf5xxx_wr_cacr(MCF5XXX_CACR_DCINVA);
    
    return 0;
}
/********************************************************************/
/*!
 * \brief   SRAM Burst Write Test
 * \param   addr SRAM test address 
 * \return  0 for pass, non-zero for failure
 *
 * Test aligned bursts to the SRAM controller.  This test uses the
 * movem instruction of the ColdFire core to burst to the memory.
 *
 * \warning This test does not perform mis-aligned burst writes. There
 *          is no bus master on the MCF5445x that is capable of bursting
 *          to the SRAM on a non-line-aligned address.
 */
int
sram_burst_write (ADDRESS addr)
{
    int i;
    uint32 lw0, lw1, lw2, lw3, *dest;

    #ifdef SRAM_DEBUG_PRINT
        printf("SRAM Burst Write Test:\n");
    #endif

    /* Initialize SRAM with known data */
    dest = (uint32*)(addr);
    for (i = 0; i < sizeof(test_data)/4; i++)
        dest[i] = 0x0;
        
    /* Burst writes */
    for (i = 0; i < sizeof(test_data); i+=16)
    {
        mcf5xxx_move_line((ADDRESS)&test_data[i/4], (ADDRESS)&dest[i/4]);
    }

    /* Verify data in SRAM */
    for (i = 0; i < sizeof(test_data)/4; i++)
    {
        if (dest[i] != test_data[i])
            return 1;
    }
    
    return 0;
}
/********************************************************************/
/*!
 * \brief   SRAM Data Bus Test
 * \param   addr SRAM test address 
 * \return  0 for success, non-zero for failure
 */
int
sram_data_test(ADDRESS address)
{
    return (memtest_databus_8((uint8*)address) || 
            memtest_databus_16((uint16*)address) || 
            memtest_databus_16((uint16*)address+1) ||
            memtest_databus_32((uint32*)address) ||
            memtest_databus_32((uint32*)address+1) ||
            memtest_databus_32((uint32*)address+2) ||
            memtest_databus_32((uint32*)address+3));
}
/********************************************************************/
/*!
 * \brief   SRAM Address Bus Test
 * \param   addr    SRAM test address 
 * \param   bytes   Number of bytes to test
 * \return  0 for success, non-zero for failure
 */
int
sram_addr_test(ADDRESS address, int bytes)
{
    return (memtest_addrbus_8((uint8*)address, bytes) ||
            memtest_addrbus_16((uint16*)address, bytes) ||
            memtest_addrbus_16((uint16*)address+1, bytes) ||
            memtest_addrbus_32((uint32*)address, bytes) ||
            memtest_addrbus_32((uint32*)address+1, bytes) ||
            memtest_addrbus_32((uint32*)address+2, bytes) ||
            memtest_addrbus_32((uint32*)address+3, bytes));
}
/********************************************************************/
/*!
 * \brief   SRAM Device Test
 * \param   addr SRAM test address 
 * \param   bytes   Number of bytes to test
 * \return  0 for success, non-zero for failure
 */
int
sram_device_test(ADDRESS address, int bytes)
{
    return (memtest_device_8((uint8*)address, bytes) ||
            memtest_device_16((uint16*)address, bytes) ||
            memtest_device_32((uint32*)address, bytes));
}
/********************************************************************/