mcf5445x_dspi.h

来自「Freescale MCF5445evb 参考测试代码」· C头文件 代码 · 共 397 行 · 第 1/2 页

#define MCF_DSPI_DCTAR3_FMSZ(x)     (((x)&0x0000000F)<<27)  /* Frame size */
#define MCF_DSPI_DCTAR3_DBR         (0x80000000)            /* Double baud rate */

/* Bit definitions and macros for DCTAR4 */
#define MCF_DSPI_DCTAR4_BR(x)       (((x)&0x0000000F))      /* Baud rate scaler */
#define MCF_DSPI_DCTAR4_DT(x)       (((x)&0x0000000F)<<4)   /* Delay after transfer scaler */
#define MCF_DSPI_DCTAR4_ASC(x)      (((x)&0x0000000F)<<8)   /* After SCK delay scaler */
#define MCF_DSPI_DCTAR4_CSSCK(x)    (((x)&0x0000000F)<<12)  /* PCS to SCK delay scaler */
#define MCF_DSPI_DCTAR4_PBR(x)      (((x)&0x00000003)<<16)  /* Baud rate prescaler */
#define MCF_DSPI_DCTAR4_PDT(x)      (((x)&0x00000003)<<18)  /* Delay after transfer prescaler */
#define MCF_DSPI_DCTAR4_PASC(x)     (((x)&0x00000003)<<20)  /* After SCK delay prescaler */
#define MCF_DSPI_DCTAR4_PCSSCK(x)   (((x)&0x00000003)<<22)  /* PCS to SCK delay prescaler */
#define MCF_DSPI_DCTAR4_LSBFE       (0x01000000)            /* LSB first enable */
#define MCF_DSPI_DCTAR4_CPHA        (0x02000000)            /* Clock phase */
#define MCF_DSPI_DCTAR4_CPOL        (0x04000000)            /* Clock polarity */
#define MCF_DSPI_DCTAR4_FMSZ(x)     (((x)&0x0000000F)<<27)  /* Frame size */
#define MCF_DSPI_DCTAR4_DBR         (0x80000000)            /* Double baud rate */

/* Bit definitions and macros for DCTAR5 */
#define MCF_DSPI_DCTAR5_BR(x)       (((x)&0x0000000F))      /* Baud rate scaler */
#define MCF_DSPI_DCTAR5_DT(x)       (((x)&0x0000000F)<<4)   /* Delay after transfer scaler */
#define MCF_DSPI_DCTAR5_ASC(x)      (((x)&0x0000000F)<<8)   /* After SCK delay scaler */
#define MCF_DSPI_DCTAR5_CSSCK(x)    (((x)&0x0000000F)<<12)  /* PCS to SCK delay scaler */
#define MCF_DSPI_DCTAR5_PBR(x)      (((x)&0x00000003)<<16)  /* Baud rate prescaler */
#define MCF_DSPI_DCTAR5_PDT(x)      (((x)&0x00000003)<<18)  /* Delay after transfer prescaler */
#define MCF_DSPI_DCTAR5_PASC(x)     (((x)&0x00000003)<<20)  /* After SCK delay prescaler */
#define MCF_DSPI_DCTAR5_PCSSCK(x)   (((x)&0x00000003)<<22)  /* PCS to SCK delay prescaler */
#define MCF_DSPI_DCTAR5_LSBFE       (0x01000000)            /* LSB first enable */
#define MCF_DSPI_DCTAR5_CPHA        (0x02000000)            /* Clock phase */
#define MCF_DSPI_DCTAR5_CPOL        (0x04000000)            /* Clock polarity */
#define MCF_DSPI_DCTAR5_FMSZ(x)     (((x)&0x0000000F)<<27)  /* Frame size */
#define MCF_DSPI_DCTAR5_DBR         (0x80000000)            /* Double baud rate */

/* Bit definitions and macros for DCTAR6 */
#define MCF_DSPI_DCTAR6_BR(x)       (((x)&0x0000000F))      /* Baud rate scaler */
#define MCF_DSPI_DCTAR6_DT(x)       (((x)&0x0000000F)<<4)   /* Delay after transfer scaler */
#define MCF_DSPI_DCTAR6_ASC(x)      (((x)&0x0000000F)<<8)   /* After SCK delay scaler */
#define MCF_DSPI_DCTAR6_CSSCK(x)    (((x)&0x0000000F)<<12)  /* PCS to SCK delay scaler */
#define MCF_DSPI_DCTAR6_PBR(x)      (((x)&0x00000003)<<16)  /* Baud rate prescaler */
#define MCF_DSPI_DCTAR6_PDT(x)      (((x)&0x00000003)<<18)  /* Delay after transfer prescaler */
#define MCF_DSPI_DCTAR6_PASC(x)     (((x)&0x00000003)<<20)  /* After SCK delay prescaler */
#define MCF_DSPI_DCTAR6_PCSSCK(x)   (((x)&0x00000003)<<22)  /* PCS to SCK delay prescaler */
#define MCF_DSPI_DCTAR6_LSBFE       (0x01000000)            /* LSB first enable */
#define MCF_DSPI_DCTAR6_CPHA        (0x02000000)            /* Clock phase */
#define MCF_DSPI_DCTAR6_CPOL        (0x04000000)            /* Clock polarity */
#define MCF_DSPI_DCTAR6_FMSZ(x)     (((x)&0x0000000F)<<27)  /* Frame size */
#define MCF_DSPI_DCTAR6_DBR         (0x80000000)            /* Double baud rate */

/* Bit definitions and macros for DCTAR7 */
#define MCF_DSPI_DCTAR7_BR(x)       (((x)&0x0000000F))      /* Baud rate scaler */
#define MCF_DSPI_DCTAR7_DT(x)       (((x)&0x0000000F)<<4)   /* Delay after transfer scaler */
#define MCF_DSPI_DCTAR7_ASC(x)      (((x)&0x0000000F)<<8)   /* After SCK delay scaler */
#define MCF_DSPI_DCTAR7_CSSCK(x)    (((x)&0x0000000F)<<12)  /* PCS to SCK delay scaler */
#define MCF_DSPI_DCTAR7_PBR(x)      (((x)&0x00000003)<<16)  /* Baud rate prescaler */
#define MCF_DSPI_DCTAR7_PDT(x)      (((x)&0x00000003)<<18)  /* Delay after transfer prescaler */
#define MCF_DSPI_DCTAR7_PASC(x)     (((x)&0x00000003)<<20)  /* After SCK delay prescaler */
#define MCF_DSPI_DCTAR7_PCSSCK(x)   (((x)&0x00000003)<<22)  /* PCS to SCK delay prescaler */
#define MCF_DSPI_DCTAR7_LSBFE       (0x01000000)            /* LSB first enable */
#define MCF_DSPI_DCTAR7_CPHA        (0x02000000)            /* Clock phase */
#define MCF_DSPI_DCTAR7_CPOL        (0x04000000)            /* Clock polarity */
#define MCF_DSPI_DCTAR7_FMSZ(x)     (((x)&0x0000000F)<<27)  /* Frame size */
#define MCF_DSPI_DCTAR7_DBR         (0x80000000)            /* Double baud rate */

/* Bit definitions and macros for DSR */
#define MCF_DSPI_DSR_RXPTR(x)   (((x)&0x0000000F))      /* Receive next pointer */
#define MCF_DSPI_DSR_RXCTR(x)   (((x)&0x0000000F)<<4)   /* Receive FIFO counter */
#define MCF_DSPI_DSR_TXPTR(x)   (((x)&0x0000000F)<<8)   /* Transmit next pointer */
#define MCF_DSPI_DSR_TXCTR(x)   (((x)&0x0000000F)<<12)  /* Transmit FIFO counter */
#define MCF_DSPI_DSR_RFDF       (0x00020000)            /* Receive FIFO drain flag */
#define MCF_DSPI_DSR_RFOF       (0x00080000)            /* Receive FIFO overflow flag */
#define MCF_DSPI_DSR_TFFF       (0x02000000)            /* Transmit FIFO fill flag */
#define MCF_DSPI_DSR_TFUF       (0x08000000)            /* Transmit FIFO underflow flag */
#define MCF_DSPI_DSR_EOQF       (0x10000000)            /* End of queue flag */
#define MCF_DSPI_DSR_TXRXS      (0x40000000)            /* Tx and Rx status (enabled | disabled) */
#define MCF_DSPI_DSR_TCF        (0x80000000)            /* Transfer complete flag */

/* Bit definitions and macros for DRSER */
#define MCF_DSPI_DRSER_RFDFS    (0x00010000)    /* Receive FIFO drain DMA or interrupt select */
#define MCF_DSPI_DRSER_RFDFE    (0x00020000)    /* Receive FIFO drain request enable */
#define MCF_DSPI_DRSER_RFOFE    (0x00080000)    /* Receive FIFO overflow request enable */
#define MCF_DSPI_DRSER_TFFFS    (0x01000000)    /* Transmit FIFO fill DMA or interrupt select */
#define MCF_DSPI_DRSER_TFFFE    (0x02000000)    /* Transmit FIFO fill request enable */
#define MCF_DSPI_DRSER_TFUFE    (0x08000000)    /* Transmit FIFO underflow request enable */
#define MCF_DSPI_DRSER_EOQFE    (0x10000000)    /* DSPI finished request enable */
#define MCF_DSPI_DRSER_TCFE     (0x80000000)    /* Transmission complete request enable */

/* Bit definitions and macros for PUSHR */
#define MCF_DSPI_PUSHR_TXDATA(x)    (((x)&0x0000FFFF))      /* Transmit data */
#define MCF_DSPI_PUSHR_PCS0         (0x00010000)            /* Peripheral chip select 0 */
#define MCF_DSPI_PUSHR_PCS1         (0x00020000)            /* Peripheral chip select 1 */
#define MCF_DSPI_PUSHR_PCS2         (0x00040000)            /* Peripheral chip select 2 */
#define MCF_DSPI_PUSHR_PCS3         (0x00080000)            /* Peripheral chip select 3 */
#define MCF_DSPI_PUSHR_PCS4         (0x00100000)            /* Peripheral chip select 4 */
#define MCF_DSPI_PUSHR_PCS5         (0x00200000)            /* Peripheral chip select 5 */
#define MCF_DSPI_PUSHR_PCS6         (0x00400000)            /* Peripheral chip select 6 */
#define MCF_DSPI_PUSHR_PCS7         (0x00800000)            /* Peripheral chip select 7 */
#define MCF_DSPI_PUSHR_CTCNT        (0x04000000)            /* Clear SPI transfer counter */
#define MCF_DSPI_PUSHR_EOQ          (0x08000000)            /* End of queue */
#define MCF_DSPI_PUSHR_CTAS(x)      (((x)&0x00000007)<<28)  /* Clock and transfer attributes select */
#define MCF_DSPI_PUSHR_CONT         (0x80000000)            /* Continuous peripheral chip-select enable */

/* Bit definitions and macros for POPR */
#define MCF_DSPI_POPR_RXDATA(x)     (((x)&0x0000FFFF))  /* Receive data */

/* Bit definitions and macros for DTFDR group */
#define MCF_DSPI_DTFDR_TXDATA(x)    (((x)&0x0000FFFF))      /* Transmit data */
#define MCF_DSPI_DTFDR_PCS0         (0x00010000)            /* Peripheral chip select 0 */
#define MCF_DSPI_DTFDR_PCS1         (0x00020000)            /* Peripheral chip select 1 */
#define MCF_DSPI_DTFDR_PCS2         (0x00040000)            /* Peripheral chip select 2 */
#define MCF_DSPI_DTFDR_PCS3         (0x00080000)            /* Peripheral chip select 3 */
#define MCF_DSPI_DTFDR_PCS4         (0x00100000)            /* Peripheral chip select 4 */
#define MCF_DSPI_DTFDR_PCS5         (0x00200000)            /* Peripheral chip select 5 */
#define MCF_DSPI_DTFDR_PCS6         (0x00400000)            /* Peripheral chip select 6 */
#define MCF_DSPI_DTFDR_PCS7         (0x00800000)            /* Peripheral chip select 7 */
#define MCF_DSPI_DTFDR_CTCNT        (0x04000000)            /* Clear SPI transfer counter */
#define MCF_DSPI_DTFDR_EOQ          (0x08000000)            /* End of queue */
#define MCF_DSPI_DTFDR_CTAS(x)      (((x)&0x00000007)<<28)  /* Clock and transfer attributes select */
#define MCF_DSPI_DTFDR_CONT         (0x80000000)            /* Continuous peripheral chip-select enable */

/* Bit definitions and macros for DTFDR0 */
#define MCF_DSPI_DTFDR0_TXDATA(x)   (((x)&0x0000FFFF))      /* Transmit data */
#define MCF_DSPI_DTFDR0_PCS0        (0x00010000)            /* Peripheral chip select 0 */
#define MCF_DSPI_DTFDR0_PCS1        (0x00020000)            /* Peripheral chip select 1 */
#define MCF_DSPI_DTFDR0_PCS2        (0x00040000)            /* Peripheral chip select 2 */
#define MCF_DSPI_DTFDR0_PCS3        (0x00080000)            /* Peripheral chip select 3 */
#define MCF_DSPI_DTFDR0_PCS4        (0x00100000)            /* Peripheral chip select 4 */
#define MCF_DSPI_DTFDR0_PCS5        (0x00200000)            /* Peripheral chip select 5 */
#define MCF_DSPI_DTFDR0_PCS6        (0x00400000)            /* Peripheral chip select 6 */
#define MCF_DSPI_DTFDR0_PCS7        (0x00800000)            /* Peripheral chip select 7 */
#define MCF_DSPI_DTFDR0_CTCNT       (0x04000000)            /* Clear SPI transfer counter */
#define MCF_DSPI_DTFDR0_EOQ         (0x08000000)            /* End of queue */
#define MCF_DSPI_DTFDR0_CTAS(x)     (((x)&0x00000007)<<28)  /* Clock and transfer attributes select */
#define MCF_DSPI_DTFDR0_CONT        (0x80000000)            /* Continuous peripheral chip-select enable */

/* Bit definitions and macros for DTFDR1 */
#define MCF_DSPI_DTFDR1_TXDATA(x)   (((x)&0x0000FFFF))      /* Transmit data */
#define MCF_DSPI_DTFDR1_PCS0        (0x00010000)            /* Peripheral chip select 0 */
#define MCF_DSPI_DTFDR1_PCS1        (0x00020000)            /* Peripheral chip select 1 */
#define MCF_DSPI_DTFDR1_PCS2        (0x00040000)            /* Peripheral chip select 2 */
#define MCF_DSPI_DTFDR1_PCS3        (0x00080000)            /* Peripheral chip select 3 */
#define MCF_DSPI_DTFDR1_PCS4        (0x00100000)            /* Peripheral chip select 4 */
#define MCF_DSPI_DTFDR1_PCS5        (0x00200000)            /* Peripheral chip select 5 */
#define MCF_DSPI_DTFDR1_PCS6        (0x00400000)            /* Peripheral chip select 6 */
#define MCF_DSPI_DTFDR1_PCS7        (0x00800000)            /* Peripheral chip select 7 */
#define MCF_DSPI_DTFDR1_CTCNT       (0x04000000)            /* Clear SPI transfer counter */
#define MCF_DSPI_DTFDR1_EOQ         (0x08000000)            /* End of queue */
#define MCF_DSPI_DTFDR1_CTAS(x)     (((x)&0x00000007)<<28)  /* Clock and transfer attributes select */
#define MCF_DSPI_DTFDR1_CONT        (0x80000000)            /* Continuous peripheral chip-select enable */

/* Bit definitions and macros for DTFDR2 */
#define MCF_DSPI_DTFDR2_TXDATA(x)   (((x)&0x0000FFFF))      /* Transmit data */
#define MCF_DSPI_DTFDR2_PCS0        (0x00010000)            /* Peripheral chip select 0 */
#define MCF_DSPI_DTFDR2_PCS1        (0x00020000)            /* Peripheral chip select 1 */
#define MCF_DSPI_DTFDR2_PCS2        (0x00040000)            /* Peripheral chip select 2 */
#define MCF_DSPI_DTFDR2_PCS3        (0x00080000)            /* Peripheral chip select 3 */
#define MCF_DSPI_DTFDR2_PCS4        (0x00100000)            /* Peripheral chip select 4 */
#define MCF_DSPI_DTFDR2_PCS5        (0x00200000)            /* Peripheral chip select 5 */
#define MCF_DSPI_DTFDR2_PCS6        (0x00400000)            /* Peripheral chip select 6 */
#define MCF_DSPI_DTFDR2_PCS7        (0x00800000)            /* Peripheral chip select 7 */
#define MCF_DSPI_DTFDR2_CTCNT       (0x04000000)            /* Clear SPI transfer counter */
#define MCF_DSPI_DTFDR2_EOQ         (0x08000000)            /* End of queue */
#define MCF_DSPI_DTFDR2_CTAS(x)     (((x)&0x00000007)<<28)  /* Clock and transfer attributes select */
#define MCF_DSPI_DTFDR2_CONT        (0x80000000)            /* Continuous peripheral chip-select enable */

/* Bit definitions and macros for DTFDR3 */
#define MCF_DSPI_DTFDR3_TXDATA(x)   (((x)&0x0000FFFF))      /* Transmit data */
#define MCF_DSPI_DTFDR3_PCS0        (0x00010000)            /* Peripheral chip select 0 */
#define MCF_DSPI_DTFDR3_PCS1        (0x00020000)            /* Peripheral chip select 1 */
#define MCF_DSPI_DTFDR3_PCS2        (0x00040000)            /* Peripheral chip select 2 */
#define MCF_DSPI_DTFDR3_PCS3        (0x00080000)            /* Peripheral chip select 3 */
#define MCF_DSPI_DTFDR3_PCS4        (0x00100000)            /* Peripheral chip select 4 */
#define MCF_DSPI_DTFDR3_PCS5        (0x00200000)            /* Peripheral chip select 5 */
#define MCF_DSPI_DTFDR3_PCS6        (0x00400000)            /* Peripheral chip select 6 */
#define MCF_DSPI_DTFDR3_PCS7        (0x00800000)            /* Peripheral chip select 7 */
#define MCF_DSPI_DTFDR3_CTCNT       (0x04000000)            /* Clear SPI transfer counter */
#define MCF_DSPI_DTFDR3_EOQ         (0x08000000)            /* End of queue */
#define MCF_DSPI_DTFDR3_CTAS(x)     (((x)&0x00000007)<<28)  /* Clock and transfer attributes select */
#define MCF_DSPI_DTFDR3_CONT        (0x80000000)            /* Continuous peripheral chip-select enable */

/* Bit definitions and macros for DRFDR group */
#define MCF_DSPI_DRFDR_RXDATA(x)    (((x)&0x0000FFFF))  /* Receive data */

/* Bit definitions and macros for DRFDR0 */
#define MCF_DSPI_DRFDR0_RXDATA(x)   (((x)&0x0000FFFF))  /* Receive data */

/* Bit definitions and macros for DRFDR1 */
#define MCF_DSPI_DRFDR1_RXDATA(x)   (((x)&0x0000FFFF))  /* Receive data */

/* Bit definitions and macros for DRFDR2 */
#define MCF_DSPI_DRFDR2_RXDATA(x)   (((x)&0x0000FFFF))  /* Receive data */

/* Bit definitions and macros for DRFDR3 */
#define MCF_DSPI_DRFDR3_RXDATA(x)   (((x)&0x0000FFFF))  /* Receive data */

/********************************************************************/

#endif /* __MCF5445X_DSPI_H__ */