mcf5445x_gpio.h

Freescale MCF5445evb 参考测试代码

/*
 * File:    mcf5445x_gpio.h
 * Purpose: Register and bit definitions
 */

#ifndef __MCF5445X_GPIO_H__
#define __MCF5445X_GPIO_H__

/*********************************************************************
*
* General Purpose I/O Module (GPIO)
*
*********************************************************************/

/* Register read/write macros */
#define MCF_GPIO_PODR_FEC0H         (*(vuint8 *)(0xFC0A4000))   /* FEC0 High Port Output Data Register */
#define MCF_GPIO_PODR_FEC0L         (*(vuint8 *)(0xFC0A4001))   /* FEC0 Low Port Output Data Register */
#define MCF_GPIO_PODR_SSI           (*(vuint8 *)(0xFC0A4002))   /* SSI Port Output Data Register */
#define MCF_GPIO_PODR_FBCTL         (*(vuint8 *)(0xFC0A4003))   /* Flexbus Control Port Output Data Register */
#define MCF_GPIO_PODR_BE            (*(vuint8 *)(0xFC0A4004))   /* Flexbus Byte Enable Port Output Data Register */
#define MCF_GPIO_PODR_CS            (*(vuint8 *)(0xFC0A4005))   /* Flexbus Chip-Select Port Output Data Register */
#define MCF_GPIO_PODR_DMA           (*(vuint8 *)(0xFC0A4006))   /* DMA Port Output Data Register */
#define MCF_GPIO_PODR_FECI2C        (*(vuint8 *)(0xFC0A4007))   /* FEC1 / I2C Port Output Data Register */
#define MCF_GPIO_PODR_UART          (*(vuint8 *)(0xFC0A4009))   /* UART Port Output Data Register */
#define MCF_GPIO_PODR_DSPI          (*(vuint8 *)(0xFC0A400A))   /* DSPI Port Output Data Register */
#define MCF_GPIO_PODR_TIMER         (*(vuint8 *)(0xFC0A400B))   /* Timer Port Output Data Register */
#define MCF_GPIO_PODR_PCI           (*(vuint8 *)(0xFC0A400C))   /* PCI Port Output Data Register */
#define MCF_GPIO_PODR_USB           (*(vuint8 *)(0xFC0A400D))   /* USB Port Output Data Register */
#define MCF_GPIO_PODR_ATAH          (*(vuint8 *)(0xFC0A400E))   /* ATA High Port Output Data Register */
#define MCF_GPIO_PODR_ATAL          (*(vuint8 *)(0xFC0A400F))   /* ATA Low Port Output Data Register */
#define MCF_GPIO_PODR_FEC1H         (*(vuint8 *)(0xFC0A4010))   /* FEC1 High Port Output Data Register */
#define MCF_GPIO_PODR_FEC1L         (*(vuint8 *)(0xFC0A4011))   /* FEC1 Low Port Output Data Register */
#define MCF_GPIO_PODR_FBADH         (*(vuint8 *)(0xFC0A4014))   /* Flexbus AD High Port Output Data Register */
#define MCF_GPIO_PODR_FBADMH        (*(vuint8 *)(0xFC0A4015))   /* Flexbus AD Med-High Port Output Data Register */
#define MCF_GPIO_PODR_FBADML        (*(vuint8 *)(0xFC0A4016))   /* Flexbus AD Med-Low Port Output Data Register */
#define MCF_GPIO_PODR_FBADL         (*(vuint8 *)(0xFC0A4017))   /* Flexbus AD Low Port Output Data Register */
#define MCF_GPIO_PDDR_FEC0H         (*(vuint8 *)(0xFC0A4018))   /* FEC0 High Port Data Direction Register */
#define MCF_GPIO_PDDR_FEC0L         (*(vuint8 *)(0xFC0A4019))   /* FEC0 Low Port Data Direction Register */
#define MCF_GPIO_PDDR_SSI           (*(vuint8 *)(0xFC0A401A))   /* SSI Port Data Direction Register */
#define MCF_GPIO_PDDR_FBCTL         (*(vuint8 *)(0xFC0A401B))   /* Flexbus Control Port Data Direction Register */
#define MCF_GPIO_PDDR_BE            (*(vuint8 *)(0xFC0A401C))   /* Flexbus Byte Enable Port Data Direction Register */
#define MCF_GPIO_PDDR_CS            (*(vuint8 *)(0xFC0A401D))   /* Flexbus Chip-Select Port Data Direction Register */
#define MCF_GPIO_PDDR_DMA           (*(vuint8 *)(0xFC0A401E))   /* DMA Port Data Direction Register */
#define MCF_GPIO_PDDR_FECI2C        (*(vuint8 *)(0xFC0A401F))   /* FEC1 / I2C Port Data Direction Register */
#define MCF_GPIO_PDDR_UART          (*(vuint8 *)(0xFC0A4021))   /* UART Port Data Direction Register */
#define MCF_GPIO_PDDR_DSPI          (*(vuint8 *)(0xFC0A4022))   /* DSPI Port Data Direction Register */
#define MCF_GPIO_PDDR_TIMER         (*(vuint8 *)(0xFC0A4023))   /* Timer Port Data Direction Register */
#define MCF_GPIO_PDDR_PCI           (*(vuint8 *)(0xFC0A4024))   /* PCI Port Data Direction Register */
#define MCF_GPIO_PDDR_USB           (*(vuint8 *)(0xFC0A4025))   /* USB Port Data Direction Register */
#define MCF_GPIO_PDDR_ATAH          (*(vuint8 *)(0xFC0A4026))   /* ATA High Port Data Direction Register */
#define MCF_GPIO_PDDR_ATAL          (*(vuint8 *)(0xFC0A4027))   /* ATA Low Port Data Direction Register */
#define MCF_GPIO_PDDR_FEC1H         (*(vuint8 *)(0xFC0A4028))   /* FEC1 High Port Data Direction Register */
#define MCF_GPIO_PDDR_FEC1L         (*(vuint8 *)(0xFC0A4029))   /* FEC1 Low Port Data Direction Register */
#define MCF_GPIO_PDDR_FBADH         (*(vuint8 *)(0xFC0A402C))   /* Flexbus AD High Port Data Direction Register */
#define MCF_GPIO_PDDR_FBADMH        (*(vuint8 *)(0xFC0A402D))   /* Flexbus AD Med-High Port Data Direction Register */
#define MCF_GPIO_PDDR_FBADML        (*(vuint8 *)(0xFC0A402E))   /* Flexbus AD Med-Low Port Data Direction Register */
#define MCF_GPIO_PDDR_FBADL         (*(vuint8 *)(0xFC0A402F))   /* Flexbus AD Low Port Data Direction Register */
#define MCF_GPIO_PPDSDR_FEC0H       (*(vuint8 *)(0xFC0A4030))   /* FEC0 High Port Pin Data/Set Data Register */
#define MCF_GPIO_PPDSDR_FEC0L       (*(vuint8 *)(0xFC0A4031))   /* FEC0 Low Port Clear Output Data Register */
#define MCF_GPIO_PPDSDR_SSI         (*(vuint8 *)(0xFC0A4032))   /* SSI Port Pin Data/Set Data Register */
#define MCF_GPIO_PPDSDR_FBCTL       (*(vuint8 *)(0xFC0A4033))   /* Flexbus Control Port Pin Data/Set Data Register */
#define MCF_GPIO_PPDSDR_BE          (*(vuint8 *)(0xFC0A4034))   /* Flexbus Byte Enable Port Pin Data/Set Data Register */
#define MCF_GPIO_PPDSDR_CS          (*(vuint8 *)(0xFC0A4035))   /* Flexbus Chip-Select Port Pin Data/Set Data Register */
#define MCF_GPIO_PPDSDR_DMA         (*(vuint8 *)(0xFC0A4036))   /* DMA Port Pin Data/Set Data Register */
#define MCF_GPIO_PPDSDR_FECI2C      (*(vuint8 *)(0xFC0A4037))   /* FEC1 / I2C Port Pin Data/Set Data Register */
#define MCF_GPIO_PPDSDR_UART        (*(vuint8 *)(0xFC0A4039))   /* UART Port Pin Data/Set Data Register */
#define MCF_GPIO_PPDSDR_DSPI        (*(vuint8 *)(0xFC0A403A))   /* DSPI Port Pin Data/Set Data Register */
#define MCF_GPIO_PPDSDR_TIMER       (*(vuint8 *)(0xFC0A403B))   /* FTimer Port Pin Data/Set Data Register */
#define MCF_GPIO_PPDSDR_PCI         (*(vuint8 *)(0xFC0A403C))   /* PCI Port Pin Data/Set Data Register */
#define MCF_GPIO_PPDSDR_USB         (*(vuint8 *)(0xFC0A403D))   /* USB Port Pin Data/Set Data Register */
#define MCF_GPIO_PPDSDR_ATAH        (*(vuint8 *)(0xFC0A403E))   /* ATA High Port Pin Data/Set Data Register */
#define MCF_GPIO_PPDSDR_ATAL        (*(vuint8 *)(0xFC0A403F))   /* ATA Low Port Pin Data/Set Data Register */
#define MCF_GPIO_PPDSDR_FEC1H       (*(vuint8 *)(0xFC0A4040))   /* FEC1 High Port Pin Data/Set Data Register */
#define MCF_GPIO_PPDSDR_FEC1L       (*(vuint8 *)(0xFC0A4041))   /* FEC1 Low Port Pin Data/Set Data Register */
#define MCF_GPIO_PPDSDR_FBADH       (*(vuint8 *)(0xFC0A4044))   /* Flexbus AD High Port Pin Data/Set Data Register */
#define MCF_GPIO_PPDSDR_FBADMH      (*(vuint8 *)(0xFC0A4045))   /* Flexbus AD Med-High Port Pin Data/Set Data Register */
#define MCF_GPIO_PPDSDR_FBADML      (*(vuint8 *)(0xFC0A4046))   /* Flexbus AD Med-Low Port Pin Data/Set Data Register */
#define MCF_GPIO_PPDSDR_FBADL       (*(vuint8 *)(0xFC0A4047))   /* Flexbus AD Low Port Pin Data/Set Data Register */
#define MCF_GPIO_PCLRR_FEC0H        (*(vuint8 *)(0xFC0A4048))   /* FEC0 High Port Clear Output Data Register */
#define MCF_GPIO_PCLRR_FEC0L        (*(vuint8 *)(0xFC0A4049))   /* FEC0 Low Port Pin Data/Set Data Register */
#define MCF_GPIO_PCLRR_SSI          (*(vuint8 *)(0xFC0A404A))   /* SSI Port Clear Output Data Register */
#define MCF_GPIO_PCLRR_FBCTL        (*(vuint8 *)(0xFC0A404B))   /* Flexbus Control Port Clear Output Data Register */
#define MCF_GPIO_PCLRR_BE           (*(vuint8 *)(0xFC0A404C))   /* Flexbus Byte Enable Port Clear Output Data Register */
#define MCF_GPIO_PCLRR_CS           (*(vuint8 *)(0xFC0A404D))   /* Flexbus Chip-Select Port Clear Output Data Register */
#define MCF_GPIO_PCLRR_DMA          (*(vuint8 *)(0xFC0A404E))   /* DMA Port Clear Output Data Register */
#define MCF_GPIO_PCLRR_FECI2C       (*(vuint8 *)(0xFC0A404F))   /* FEC1 / I2C Port Clear Output Data Register */
#define MCF_GPIO_PCLRR_UART         (*(vuint8 *)(0xFC0A4051))   /* UART Port Clear Output Data Register */
#define MCF_GPIO_PCLRR_DSPI         (*(vuint8 *)(0xFC0A4052))   /* DSPI Port Clear Output Data Register */
#define MCF_GPIO_PCLRR_TIMER        (*(vuint8 *)(0xFC0A4053))   /* Timer Port Clear Output Data Register */
#define MCF_GPIO_PCLRR_PCI          (*(vuint8 *)(0xFC0A4054))   /* PCI Port Clear Output Data Register */
#define MCF_GPIO_PCLRR_USB          (*(vuint8 *)(0xFC0A4055))   /* USB Port Clear Output Data Register */
#define MCF_GPIO_PCLRR_ATAH         (*(vuint8 *)(0xFC0A4056))   /* ATA High Port Clear Output Data Register */
#define MCF_GPIO_PCLRR_ATAL         (*(vuint8 *)(0xFC0A4057))   /* ATA Low Port Clear Output Data Register */
#define MCF_GPIO_PCLRR_FEC1H        (*(vuint8 *)(0xFC0A4058))   /* FEC1 High Port Clear Output Data Register */
#define MCF_GPIO_PCLRR_FEC1L        (*(vuint8 *)(0xFC0A4059))   /* FEC1 Low Port Clear Output Data Register */
#define MCF_GPIO_PCLRR_FBADH        (*(vuint8 *)(0xFC0A405C))   /* Flexbus AD High Port Clear Output Data Register */
#define MCF_GPIO_PCLRR_FBADMH       (*(vuint8 *)(0xFC0A405D))   /* Flexbus AD Med-High Port Clear Output Data Register */
#define MCF_GPIO_PCLRR_FBADML       (*(vuint8 *)(0xFC0A405E))   /* Flexbus AD Med-Low Port Clear Output Data Register */
#define MCF_GPIO_PCLRR_FBADL        (*(vuint8 *)(0xFC0A405F))   /* Flexbus AD Low Port Clear Output Data Register */
#define MCF_GPIO_PAR_FEC            (*(vuint8 *)(0xFC0A4060))   /* FEC Pin Assignment Register */
#define MCF_GPIO_PAR_DMA            (*(vuint8 *)(0xFC0A4061))   /* DMA Pin Assignment Register */
#define MCF_GPIO_PAR_FBCTL          (*(vuint8 *)(0xFC0A4062))   /* Flexbus Control Pin Assignment Register */
#define MCF_GPIO_PAR_DSPI           (*(vuint8 *)(0xFC0A4063))   /* DSPI Pin Assignment Register */
#define MCF_GPIO_PAR_BE             (*(vuint8 *)(0xFC0A4064))   /* Flexbus Byte-Enable Pin Assignment Register */
#define MCF_GPIO_PAR_CS             (*(vuint8 *)(0xFC0A4065))   /* Flexbus Chip-Select Pin Assignment Register */
#define MCF_GPIO_PAR_TIMER          (*(vuint8 *)(0xFC0A4066))   /* Time Pin Assignment Register */
#define MCF_GPIO_PAR_USB            (*(vuint8 *)(0xFC0A4067))   /* USB Pin Assignment Register */
#define MCF_GPIO_PAR_UART           (*(vuint8 *)(0xFC0A4069))   /* UART Pin Assignment Register */
#define MCF_GPIO_PAR_FECI2C         (*(vuint16*)(0xFC0A406A))   /* FEC / I2C Pin Assignment Register */
#define MCF_GPIO_PAR_SSI            (*(vuint16*)(0xFC0A406C))   /* SSI Pin Assignment Register */
#define MCF_GPIO_PAR_ATA            (*(vuint16*)(0xFC0A406E))   /* ATA Pin Assignment Register */
#define MCF_GPIO_PAR_IRQ            (*(vuint8 *)(0xFC0A4070))   /* IRQ Pin Assignment Register */
#define MCF_GPIO_PAR_PCI            (*(vuint16*)(0xFC0A4072))   /* PCI Pin Assignment Register */
#define MCF_GPIO_MSCR_SDRAM         (*(vuint8 *)(0xFC0A4074))   /* SDRAM Mode Select Control Register */
#define MCF_GPIO_MSCR_PCI           (*(vuint8 *)(0xFC0A4075))   /* PCI Mode Select Control Register */
#define MCF_GPIO_DSCR_I2C           (*(vuint8 *)(0xFC0A4078))   /* I2C Drive Strength Control Register */
#define MCF_GPIO_DSCR_FLEXBUS       (*(vuint8 *)(0xFC0A4079))   /* FLEXBUS Drive Strength Control Register */
#define MCF_GPIO_DSCR_FEC           (*(vuint8 *)(0xFC0A407A))   /* FEC Drive Strength Control Register */
#define MCF_GPIO_DSCR_UART          (*(vuint8 *)(0xFC0A407B))   /* UART Drive Strength Control Register */
#define MCF_GPIO_DSCR_DSPI          (*(vuint8 *)(0xFC0A407C))   /* DSPI Drive Strength Control Register */
#define MCF_GPIO_DSCR_TIMER         (*(vuint8 *)(0xFC0A407D))   /* TIMER Drive Strength Control Register */
#define MCF_GPIO_DSCR_SSI           (*(vuint8 *)(0xFC0A407E))   /* SSI Drive Strength Control Register */
#define MCF_GPIO_DSCR_DMA           (*(vuint8 *)(0xFC0A407F))   /* DMA Drive Strength Control Register */
#define MCF_GPIO_DSCR_DEBUG         (*(vuint8 *)(0xFC0A4080))   /* DEBUG Drive Strength Control Register */
#define MCF_GPIO_DSCR_RESET         (*(vuint8 *)(0xFC0A4081))   /* RESET Drive Strength Control Register */
#define MCF_GPIO_DSCR_IRQ           (*(vuint8 *)(0xFC0A4082))   /* IRQ Drive Strength Control Register */
#define MCF_GPIO_DSCR_USB           (*(vuint8 *)(0xFC0A4083))   /* USB Drive Strength Control Register */
#define MCF_GPIO_DSCR_ATA           (*(vuint8 *)(0xFC0A4084))   /* ATA Drive Strength Control Register */

/* Bit definitions and macros for PODR_FEC0H */
#define MCF_GPIO_PODR_FEC0H_PODR0   (0x01)  /* FEC0_CRS / ULPI_DATA6 */
#define MCF_GPIO_PODR_FEC0H_PODR1   (0x02)  /* FEC0_RXD0 / FEC0_RMII_RXD0 */
#define MCF_GPIO_PODR_FEC0H_PODR2   (0x04)  /* FEC0_RXDV / FEC0_RMII_CRS_DV */
#define MCF_GPIO_PODR_FEC0H_PODR3   (0x08)  /* FEC0_RXCLK / ULPI_DATA1 */
#define MCF_GPIO_PODR_FEC0H_PODR4   (0x10)  /* FEC0_COL / ULPI_DATA7 */
#define MCF_GPIO_PODR_FEC0H_PODR5   (0x20)  /* FEC0_TXD0 / FEC0_RMII_TXD0 */
#define MCF_GPIO_PODR_FEC0H_PODR6   (0x40)  /* FEC0_TXEN / FEC0_RMII_TXEN */
#define MCF_GPIO_PODR_FEC0H_PODR7   (0x80)  /* FEC0_TXCLK / FEC0_RMII_REF_CLK */

/* Bit definitions and macros for PODR_FEC0L */
#define MCF_GPIO_PODR_FEC0L_PODR0   (0x01)  /* FEC0_RXER / FEC0_RMII_RXER */
#define MCF_GPIO_PODR_FEC0L_PODR1   (0x02)  /* FEC0_RXD1 / FEC0_RMII_RXD1 */
#define MCF_GPIO_PODR_FEC0L_PODR2   (0x04)  /* FEC0_RXD2 / ULPI_DATA4 */
#define MCF_GPIO_PODR_FEC0L_PODR3   (0x08)  /* FEC0_RXD3 / ULPI_DATA5 */
#define MCF_GPIO_PODR_FEC0L_PODR4   (0x10)  /* FEC0_TXER / ULPI_DATA0 */
#define MCF_GPIO_PODR_FEC0L_PODR5   (0x20)  /* FEC0_TXD1 / FEC0_RMII_TXD1 */
#define MCF_GPIO_PODR_FEC0L_PODR6   (0x40)  /* FEC0_TXD2 / ULPI_DATA2 */
#define MCF_GPIO_PODR_FEC0L_PODR7   (0x80)  /* FEC0_TXD3 / ULPI_DATA3 */

/* Bit definitions and macros for PODR_SSI */
#define MCF_GPIO_PODR_SSI_PODR0     (0x01)  /* SSI_TXD / U1TXD */
#define MCF_GPIO_PODR_SSI_PODR1     (0x02)  /* SSI_RXD / U1RXD */
#define MCF_GPIO_PODR_SSI_PODR2     (0x04)  /* SSI_FS / U1RTS */
#define MCF_GPIO_PODR_SSI_PODR3     (0x08)  /* SSI_BCLK / U1CTS */
#define MCF_GPIO_PODR_SSI_PODR4     (0x10)  /* SSI_MCLK */

/* Bit definitions and macros for PODR_FBCTL */
#define MCF_GPIO_PODR_FBCTL_PODR0   (0x01)  /* FB_TS / FB_ALE / FB_TBST */
#define MCF_GPIO_PODR_FBCTL_PODR1   (0x02)  /* FB_RW */
#define MCF_GPIO_PODR_FBCTL_PODR2   (0x04)  /* FB_TA */
#define MCF_GPIO_PODR_FBCTL_PODR3   (0x08)  /* FB_OE */

/* Bit definitions and macros for PODR_BE */
#define MCF_GPIO_PODR_BE_PODR0      (0x01)  /* FB_BE/BWE0 / FB_SIZ0 */
#define MCF_GPIO_PODR_BE_PODR1      (0x02)  /* FB_BE/BWE1 / FB_SIZ1 */
#define MCF_GPIO_PODR_BE_PODR2      (0x04)  /* FB_BE/BWE2 / FB_SIZ2 */
#define MCF_GPIO_PODR_BE_PODR3      (0x08)  /* FB_BE/BWE3 / FB_SIZ3 */

/* Bit definitions and macros for PODR_CS */
#define MCF_GPIO_PODR_CS_PODR1      (0x02)  /* FB_CS1 */
#define MCF_GPIO_PODR_CS_PODR2      (0x04)  /* FB_CS2 */
#define MCF_GPIO_PODR_CS_PODR3      (0x08)  /* FB_CS3 */

/* Bit definitions and macros for PODR_DMA */
#define MCF_GPIO_PODR_DMA_PODR0     (0x01)  /* DREQ0 */
#define MCF_GPIO_PODR_DMA_PODR1     (0x02)  /* DACK0 / DSPI_PCS3 */
#define MCF_GPIO_PODR_DMA_PODR2     (0x04)  /* DREQ1 / USB_CLKIN */
#define MCF_GPIO_PODR_DMA_PODR3     (0x08)  /* DACK1 / ULPI_DIR */

/* Bit definitions and macros for PODR_FECI2C */
#define MCF_GPIO_PODR_FECI2C_PODR0      (0x01)  /* I2C_SDA / U2RXD */
#define MCF_GPIO_PODR_FECI2C_PODR1      (0x02)  /* I2C_SCL / U2TXD */
#define MCF_GPIO_PODR_FECI2C_PODR2      (0x04)  /* FEC0_MDIO */
#define MCF_GPIO_PODR_FECI2C_PODR3      (0x08)  /* FEC0_MDC */
#define MCF_GPIO_PODR_FECI2C_PODR4      (0x10)  /* FEC1_MDIO / ATA_DIOW */
#define MCF_GPIO_PODR_FECI2C_PODR5      (0x20)  /* FEC1_MDC / ATA_DIOR */

/* Bit definitions and macros for PODR_UART */
#define MCF_GPIO_PODR_UART_PODR0    (0x01)  /* U1TXD */
#define MCF_GPIO_PODR_UART_PODR1    (0x02)  /* U1RXD */
#define MCF_GPIO_PODR_UART_PODR2    (0x04)  /* U1RTS */
#define MCF_GPIO_PODR_UART_PODR3    (0x08)  /* U0CTS */
#define MCF_GPIO_PODR_UART_PODR4    (0x10)  /* U1TXD */
#define MCF_GPIO_PODR_UART_PODR5    (0x20)  /* U1RXD */
#define MCF_GPIO_PODR_UART_PODR6    (0x40)  /* U1RTS */
#define MCF_GPIO_PODR_UART_PODR7    (0x80)  /* U1CTS */

/* Bit definitions and macros for PODR_DSPI */
#define MCF_GPIO_PODR_DSPI_PODR0    (0x01)  /* DSPI_SOUT / SBF_DO */
#define MCF_GPIO_PODR_DSPI_PODR1    (0x02)  /* DSPI_SIN / SBF_DI */
#define MCF_GPIO_PODR_DSPI_PODR2    (0x04)  /* DSPI_SCK / SBF_CK */
#define MCF_GPIO_PODR_DSPI_PODR3    (0x08)  /* DSPI_PCS0/SS */
#define MCF_GPIO_PODR_DSPI_PODR4    (0x10)  /* DSPI_PCS1 / SBF_CS */
#define MCF_GPIO_PODR_DSPI_PODR5    (0x20)  /* DSPI_PCS2 */
#define MCF_GPIO_PODR_DSPI_PODR6    (0x40)  /* DSPI_PCS5/SS */

/* Bit definitions and macros for PODR_TIMER */
#define MCF_GPIO_PODR_TIMER_PODR0   (0x01)  /* T0IN / T0OUT / U2RTS */
#define MCF_GPIO_PODR_TIMER_PODR1   (0x02)  /* T1IN / T1OUT / U2CTS */
#define MCF_GPIO_PODR_TIMER_PODR2   (0x04)  /* T2IN / T2OUT / U2TXD */
#define MCF_GPIO_PODR_TIMER_PODR3   (0x08)  /* T3IN / T3OUT / U2RXD */

/* Bit definitions and macros for PODR_PCI */