pci.h

Freescale MCF5445evb 参考测试代码

#ifndef INCpcih
#define INCpcih


typedef struct pci_device
{
    uint16   vendorId;      /* vendor ID */
    uint16   deviceId;      /* device ID */
    uint16   command;       /* command register */
    uint16   status;        /* status register */
    uint8    revisionId;    /* revision ID */
    uint8    classCode; /* class code */
    uint8    subClass;      /* sub class code */
    uint8    progIf;        /* programming interface */
    uint8    cacheLine; /* cache line */
    uint8    latency;       /* latency time */
    uint8    headerType;    /* header type */
    uint8    bist;          /* BIST */
    uint32   base0;     /* base address 0 */
    uint32   base1;     /* base address 1 */
    uint32   base2;     /* base address 2 */
    uint32   base3;     /* base address 3 */
    uint32   base4;     /* base address 4 */
    uint32   base5;     /* base address 5 */
    uint32   cis;           /* cardBus CIS pointer */
    uint16   subVendorId;   /* sub system vendor ID */
    uint16   subSystemId;   /* sub system ID */
    uint32   romBase;       /* expansion ROM base address */
    uint32   reserved0; /* reserved */
    uint32   reserved1; /* reserved */
    uint8    intLine;       /* interrupt line */
    uint8    intPin;        /* interrupt pin */
    uint8    minGrant;      /* min Grant */
    uint8    maxLatency;    /* max Latency */
} pci_device;

#define PCI_MAX_PKT_SIZE            0xF000

/* 548x/7x target info */ 
#define PCI_TARG0_NUM               0
#define PCI_TARG0_BAR0              0x40000000
#define PCI_TARG0_BAR1              0x00000000
#define PCI_TARG0_INT               6
#define PCI_TARG0_IDSEL             16

/* The rest of the Targets */
#define PCI_TARG1_NUM               1
#define PCI_TARG1_BAR0              0xA0000000
#define PCI_TARG1_BAR1              0xA1000000
#define PCI_TARG1_BAR2              0xA8001000
#define PCI_TARG1_INT               6
#define PCI_TARG1_IDSEL             17

#define PCI_TARG2_NUM               2
#define PCI_TARG2_BAR0              0xA2000000
#define PCI_TARG2_BAR1              0xA3000000
#define PCI_TARG2_INT               5
#define PCI_TARG2_IDSEL             18

#define PCI_TARG3_NUM               3
#define PCI_TARG3_BAR0              0xA4000000
#define PCI_TARG3_BAR1              0xA5000000
#define PCI_TARG3_INT               6
#define PCI_TARG3_IDSEL             19

#define PCI_TARG4_NUM               3
#define PCI_TARG4_BAR0              0xA6000000
#define PCI_TARG4_BAR1              0xA7000000
#define PCI_TARG4_INT               6
#define PCI_TARG4_IDSEL             20



/* Defines Internal 548x/7x memory translation */
#if 0
#define PCI_HOST_MEM                0xC0000000
#define PCI_HOST_IO                 0xC8000000
#define PCI_HOST_CFG                0xCF000000
#else
#define PCI_HOST_MEM                0xA0000000
#define PCI_HOST_IO                 0xA8000000
#define PCI_HOST_CFG                0xAF000000

#endif

/*! PCI error code: No error */
#define PCI_OK          0
/*! PCI error code: Error in the parameters */
#define PCI_ERR_PARM    1
/*! PCI eror code: No (matching) device */
#define PCI_NO_DEV      2

/*! Number of PCI slots */
#define PCI_NUM_SLOTS   4
/*! PCI slot 0 */
#define PCI_SLOT0       16
/*! PCI slot 1 */
#define PCI_SLOT1       17
/*! PCI slot 2 */
#define PCI_SLOT2       18
/*! PCI slot 3 */
#define PCI_SLOT3       20
/*! PCI slot 4 */
#define PCI_SLOT4       21


/*! PCI mode: Configuration access */
#define PCI_MODE_CONF       0
/*! PCI mode: IO access */
#define PCI_MODE_IO         1
/*! PCI mode: Read */
#define PCI_MODE_READ       2
/*! PCI mode: Read line */
#define PCI_MODE_READLINE   3
/*! PCI mode: Read multiple */
#define PCI_MODE_READMULT   4
/*! PCI mode: Window disabled */
#define PCI_MODE_DISABLED   5


void printpciheaderinfo(int slot);
unsigned int swap32(unsigned int data);
unsigned short swap16(unsigned short data);


void initPci(void);
void pciInitDevices(void);


 
#endif /* INCpcih */