palladium.cfg

Freescale MCF5445evb 参考测试代码

ResetHalt

;Turn on RAMBAR1 at address 80000000 
writecontrolreg 0x0C05 0x80000221

;Init CS0
writemem.l 0xFC008000 0x00000000;
writemem.l 0xFC008008 0x00001D20;
writemem.l 0xFC008004 0x01FF0001;
;Init CS1
writemem.l 0xFC00800C 0x02000000;
writemem.l 0xFC008014 0x00001D20;
writemem.l 0xFC008010 0x01FF0001;
;Init CS2
writemem.l 0xFC008018 0x04000000;
writemem.l 0xFC008020 0x00001D20;
writemem.l 0xFC00801C 0x01FF0001;
;Init CS3
writemem.l 0xFC008024 0x06000000;
writemem.l 0xFC00802C 0x00001D20;
writemem.l 0xFC008028 0x01FF0001;
;Init CS4
writemem.l 0xFC008030 0x08000000;
writemem.l 0xFC008038 0x00001D20;
writemem.l 0xFC008034 0x01FF0001;
;Init CS5
writemem.l 0xFC00803C 0x0A000000;
writemem.l 0xFC008044 0x00001D20;
writemem.l 0xFC008040 0x01FF0001;


;SDRAM Initialization

delay 100

writemem.l 0xFC0B8110	0x40000018  ; SDCS0 

writemem.l 0xFC0B8008	0x33633F30  ; SDCFG1
writemem.l 0xFC0B800C	0x34470000  ; SDCFG2

; Issue PALL
writemem.l 0xFC0B8004	0xE0092002  ; SDCR


; Issue LEMR
writemem.l 0xFC0B8000	0x40010000  ; SDMR

; Write mode register
writemem.l 0xFC0B8000	0x058D0000  ; SDMR


; Wait a bit
delay 1000

; Issue PALL
writemem.l 0xFC0B8004	0xE0092002  ; SDCR


; Perform two refresh cycles
writemem.l 0xFC0B8004	0xE0092004  ; SDCR
writemem.l 0xFC0B8004	0xE0092004  ; SDCR

writemem.l 0xFC0B8000	0x018D0000  ; SDMR


writemem.l 0xFC0B8004	0x70092F00  ; SDCR


; Wait a bit
delay 100