📄 jamaica_sdram_266.cfg
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ResetHalt;Turn on RAMBAR1 at address 80000000 writecontrolreg 0x0C05 0x80000221;Init CS0 - Turn off global chip-selectwritemem.l 0xFC008004 0x00000001;;Init CS2 - CPLD @ 0x0800_0000writemem.l 0xFC008018 0x08000000;writemem.l 0xFC008020 0x00000000;writemem.l 0xFC00801C 0x00000001;;Init CS3 - FPGA @ 0x0900_0000writemem.l 0xFC008024 0x09000000;writemem.l 0xFC00802C 0x00000020;writemem.l 0xFC008028 0x00000001;;SDRAM Initialization for 266MHzdelay 100writemem.b 0xFC0A4074 0xAA ; MSCR_SDRAMwritemem.l 0xFC0B8110 0x4000001A ; SDCS0 writemem.l 0xFC0B8114 0x4800001A ; SDCS1writemem.l 0xFC0B8008 0x65311810 ; SDCFG1writemem.l 0xFC0B800C 0x59670000 ; SDCFG2writemem.l 0xFC0B8004 0xEA0F2002 ; SDCR, issue PALLwritemem.l 0xFC0B8000 0x40010408 ; SDMR, write ext mode regwritemem.l 0xFC0B8000 0x00010333 ; SDMR, write mode regdelay 1000writemem.l 0xFC0B8004 0xEA0F2002 ; SDCR, issue PALLwritemem.l 0xFC0B8004 0xEA0F2004 ; SDCR, refreshwritemem.l 0xFC0B8004 0xEA0F2004 ; SDCR, refreshwritemem.l 0xFC0B8000 0x00010233 ; SDMR, clear DLL resetwritemem.l 0xFC0B8004 0x7A0F2C00 ; SDCR, clear mode_endelay 100 ; set ref_en & dqs_oe;Point VBR to SDRAMwritecontrolreg 0x0801 0x40000000⌨️ 快捷键说明
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