jamaica_sdram_200.cfg

来自「Freescale MCF5445evb 参考测试代码」· CFG 代码 · 共 38 行

ResetHalt

;Turn on RAMBAR1 at address 80000000 
writecontrolreg 0x0C05 0x80000221

;Init CS0 - Flash0 @ 0x0400_0000
writemem.l 0xFC008000 0x04000000;
writemem.l 0xFC008008 0x00001140;
writemem.l 0xFC008004 0x00070001;

;Init CS2 - CPLD @ 0x0800_0000
writemem.l 0xFC008018 0x08000000;
writemem.l 0xFC008020 0x00000000;
writemem.l 0xFC00801C 0x00000001;

;Init CS3 - FPGA @ 0x0900_0000
writemem.l 0xFC008024 0x09000000;
writemem.l 0xFC00802C 0x00000020;
writemem.l 0xFC008028 0x00000001;

;SDRAM Initialization for 200MHz
delay 100
writemem.b 0xFC0A4074  0xAA        ; MSCR_SDRAM
writemem.l 0xFC0B8110  0x4000001A  ; SDCS0 
writemem.l 0xFC0B8114  0x4800001A  ; SDCS1
writemem.l 0xFC0B8008  0x65311610  ; SDCFG1
writemem.l 0xFC0B800C  0x59670000  ; SDCFG2
writemem.l 0xFC0B8004  0xEA0B2002  ; SDCR, issue PALL
writemem.l 0xFC0B8000  0x40010408  ; SDMR, write ext mode reg
writemem.l 0xFC0B8000  0x00010333  ; SDMR, write mode reg
delay 1000
writemem.l 0xFC0B8004  0xEA0B2002  ; SDCR, issue PALL
writemem.l 0xFC0B8004  0xEA0B2004  ; SDCR, refresh
writemem.l 0xFC0B8004  0xEA0B2004  ; SDCR, refresh
writemem.l 0xFC0B8000  0x00010233  ; SDMR, clear DLL reset
writemem.l 0xFC0B8004  0x7A0B2C00  ; SDCR, clear mode_en
delay 100                          ; set ref_en & dqs_oe