m54451evb_sdram.cfg

来自「Freescale MCF5445evb 参考测试代码」· CFG 代码 · 共 26 行

ResetHalt

;Turn on RAMBAR1 at address 80000000 
writecontrolreg 0x0C05 0x80000221

;Init CS0 - Flash @ 0x0000_0000
writemem.l 0xFC008000 0x04000000;
writemem.l 0xFC008008 0x00001140;
writemem.l 0xFC008004 0x00070001;

;SDRAM Initialization for 240MHz low-power DDR
delay 100
writemem.b 0xFC0A4074  0x55        ; MSCR_SDRAM
writemem.l 0xFC0B8110  0x4000001A  ; SDCS0 
writemem.l 0xFC0B8008  0x43822D30  ; SDCFG1
writemem.l 0xFC0B800C  0x34470000  ; SDCFG2
writemem.l 0xFC0B8004  0xE20A2C00  ; SDCR
delay 100
writemem.l 0xFC0B8004  0xE20A2C02  ; SDCR, issue PALL
writemem.l 0xFC0B8004  0xE20A2C04  ; SDCR, refresh
writemem.l 0xFC0B8004  0xE20A2C04  ; SDCR, refresh
writemem.l 0xFC0B8000  0x00CD0000  ; SDMR, DDR mode Normal, Sequential, CL=3
writemem.l 0xFC0B8000  0x80010000  ; SDMR, 4 burst, fll strength drive
writemem.l 0xFC0B8004  0x720A2C00  ; SDCR, clear mode_en, set ref_en & dqs_oe
delay 100